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研究生:古紹泓
研究生(外文):Shaw-Hung Gu
論文名稱:氮化矽快閃式記憶元件可靠度之探討
論文名稱(外文):Investigation of Reliability Issues in Nitride Trap Storage Flash Memory
指導教授:汪大暉
指導教授(外文):Tahui Wang
學位類別:博士
校院名稱:國立交通大學
系所名稱:電子工程系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:95
語文別:英文
論文頁數:140
中文關鍵詞:氮化矽快閃式記憶元件耐久性電荷幫浦量測寫入電荷水平分佈抹除狀態臨界電壓不穩定讀取擾動
外文關鍵詞:SONOS-type trapping storage flash memoriesEnduranceCharge pumping techniqueProgrammed charge lateral distributionErase-Vt state threshold voltage instabilityRead-disturb
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本篇論文主要著重在研究以氮化矽(SiN)為電荷儲存之快閃式記憶元件可靠性議題(reliability issue)研究。一般而言,為了增加電荷保存能力(retentivity),此元件通常選用較厚的底部氧化層(bottom oxide)。元件在未加壓之前,其具有相當優異的可靠度。然而,當經過多次寫入/抹除(program/erase)後,會使得氧化層造成傷害,進而對元件可靠性造成極大的影響。

第一章簡介此元件基本的結構以及寫入抹除的方式。對於二位元操作時反向讀取(reverse reading)的原理,也詳列於其中。第二章探討元件耐久性(endurance)機制。吾人發現,無論在寫入或抹除狀態之臨界電壓準位,皆會隨著寫入/抹除次數的增加而皆有向上揚升的現象。

第三章詳述一改良後之電荷幫浦(charge pumping)量測方法。藉由此法,在汲極/源極接面上之寫入電荷水平分佈,可獨立被萃取出來。吾人研究發現,在同一元件中,第二寫入的位元有著比第一寫入位元較寬的電荷分佈。此原因為在寫入第二位元時,第一寫入位元產生的電場會加速通道電子使其提早注入氮化矽層中。另外,實驗結果顯示,寫入電荷分佈會隨著寫入抹除次數增加而延伸到通道中央。

第四章中,吾人對抹除狀態臨界電壓不穩定(threshold voltage instability)、讀取擾動(read-disturb),以及寫入狀態資料流失(charge loss)有著深入的探討。首先,對於一經加壓後的元件,抹除狀態之臨界電壓會隨著儲存時間而上升。此漂移現象與溫度有著微弱的關係並且隨寫入抹除次數呈現奇特的轉彎現象(turn-around),這與底部氧化層中帶正電性缺陷的生成有著密切關係。吾人實驗結果發現,此臨界電壓漂移與時間呈現對數(logarithm)的相依性,並可用穿隧波前(tunneling front)模型來做描述。此外,若是讀取偏壓太大,正電性電荷幫助穿隧(PCAT)效應將會主導臨界電壓漂移,與時間將會轉變成指數(power-law)關係。藉由研究垂直電場以及溫度對氮化矽層電荷遺失之影響,吾人提出一解析之物理模型:Frenkel-Poole蒸散進而透過氧化層缺陷穿隧。吾人可利用此模型提出一閘極偏壓加速測試元件資料保存時間之方法。

第五章探討底部氧化層厚度以及加壓效應對於氮化矽記憶元件資料流失的影響。根據多電子捕捉(multiple electron trapping)模型,吾人利用一數值分析方法,分別對底部氧化層厚度為1.8nm到5.0nm的元件模擬其電荷保存特性。在吾人的模型中,假設氮化矽中缺陷為連續性的分佈。傳導帶(conduction band)與氮化矽中缺陷狀態(trap state)的暫態行為,可用一連串Frenkel-Poole激發以及電子再度被捕陷(re-capture)來描述。電荷流失可分為兩種途徑:一是傳導帶電子透過正電性氧化層缺陷而流失;二是電子直接穿隧過底部氧化層而散失。透過大面積元件量測,吾人發現在較厚的底部氧化層元件中,經由加壓後引致的電荷逸失現象呈現兩階段(two stages)發展。第一階段電荷漏電流被氧化層缺陷幫助穿隧給限制住。第二階段中,因Frenkel-Poole散失使其而遵循1/t的時間關係。從第一階段到第二階段之間的過渡時間與氧化層缺陷幫助穿隧時間有關,但是將會被延長一個特定比例。基於以上的了解,吾人在第六章中,利用此1/t暫態電流,萃取出氮化矽材料中缺陷的密度。

第七章中,吾人針對一局部儲存(localized storage)、多準位(multi-level)氮化矽快閃式記憶元件中,因寫入/抹除加壓後產生隨機電報雜訊(random telegraph noise, RTN)導致之讀取電流擾動作一深入之探討。吾人發現,局部儲存方式明顯地增加RTN的擾動。而RTN的振幅隨著不同的寫入準位而改變。用一機率模型,可定義此RTN造成的讀取電流擾動分佈。例外,利用較好的底部氧化層製程方法,可有效降低此讀取電流雜訊。

最後於第八章,吾人將對本論文做個總結。
This thesis will focus on the reliability issues of SONOS-type trapping storage flash memories. For today’s SONOS cells, a thicker bottom oxide is employed to improve the retentivity. These cells exhibit excellent data retention behavior before stress. After P/E cycling, the bottom oxide is damaged, thereby degrading the reliability.

In Chapter 1, the device structure and program/erase methods of the cell are described. A reverse read scheme for two-bit operation is illustrated. With respect to the cell endurance, the threshold voltage in program-state or in erase-state may shift upward as P/E cycle number increases. The mechanism will be investigated in Chapter 2.

To expound the second-bit effect, a modified charge pumping technique to characterize programmed charge lateral distribution is proposed in Chapter 3. The stored charge distribution of each bit over the source/drain junctions can be profiled separately. Our result shows that the secondly programmed bit has a broader stored charge distribution than the first programmed bit. The reason is that a large channel field exists under the first programmed bit during the second bit programming. Such a large field accelerates channel electrons and causes earlier electron injection into the nitride. In addition, we find that programmed charges spread further into the channel as program/erase cycle number increases.

Reliability issues including erase-Vt state threshold voltage instability, read-disturb, and high-Vt state charge loss will be addressed in Chapter 4. First, an erase-state threshold drift with storage time is observed in a P/E cycled cell. This drift has insignificant temperature dependence and exhibits an anomalous turn-around with P/E cycle number. This peculiar phenomenon is strongly related to the creation of positive charged defects in the bottom oxide. The temporal evolution of the threshold voltage drift has log(t) dependence on storage time and can be well described by the tunneling front model. Furthermore, at a sufficiently large read bias, positive charge assisted channel electron tunneling dominates the threshold voltage shift, causing a power-law time relation. By measuring the dependence of electric field and temperature, an analytical model based on Frenkel-Poole emission followed by oxide trap assisted tunneling successfully identifies the mechanism for charge loss. With use this model, a Vg acceleration method for retention lifetime test is also proposed.
Bottom oxide thickness and program/erase stress effects on charge retention in SONOS flash memory cells with FN programming are investigated. Utilizing a numerical analysis based on a multiple electron trapping model, the electron retention behavior in a SONOS cell with bottom oxide thickness from 1.8nm to 5.0nm is simulated. In our model, the nitride traps have a continuous energy distribution. A series of Frenkel-Poole excitation of trapped electrons to the conduction band and electron re-capture into nitride traps feature the transitions between the conduction band and trap states. Conduction band electron tunneling via positively charged oxide traps created by high-voltage stress and trapped electron direct tunneling through the bottom oxide is included to describe various charge leakage paths. We measure the nitride charge leakage current directly in a large area device for comparison. Our study reveals that the charge retention loss in a high-voltage stressed cell with a thicker bottom oxide (5nm) exhibits two stages. The charge leakage current is limited by oxide trap assisted tunneling in the first stage and then follows a 1/t time dependence due to the Frenkel-Poole emission in the second stage. The transition time from the first stage to the second stage is related to oxide trap assisted tunneling time, but is prolonged by a factor. According to the above understanding, the silicon nitride trap density can be extracted from the 1/t transient current in Chapter 6.

In Chapter 7, program/erase stress induced read current fluctuation arising from random telegraph noise (RTN) in a localized, multi-level SONOS cells is explored. Our study shows that localized charge storage significantly enhances RTN. The amplitude of RTN varies in different program levels of a multi-level cell. The broadening of read current distribution caused by RTN is characterized and modeled. Better bottom oxide process can reduce read current noise.

Conclusions are finally made in Chapter 8.
Chinese Abstract i
English Abstract iii
Acknowledgements vii
Contents ix
Table Captions xii
Figure Captions xiii
List of Symbols xxii
Chapter 1 Introduction 1
1.1 Background 1
1.2 Uniform charge storage versus localized charge storage 2
1.3 Organization of the Dissertation 5

Chapter 2 Program/Erase Cycling Induced Endurance Degradation in Nitride Storage Flash Memory Cell 12
2.1 Introduction 12
2.2 Endurance Failure in Nbit Cells 12
2.3 Evidence of Negative Charge Creation 13
2.4 Improvement of Cycling Endurance 15

Chapter 3 Characterization of Programmed Charge Lateral Distribution in Nbit Flash Memory Cell by Using Charge Pumping Technique 23
3.1 Introduction 23
3.2 Device Structure and Measurement Setup 24
3.3 Measurement Result and Discussion 25
3.3.1 Single-bit Storage 25
3.3.2 Two-bit Storage 26
3.3.3 P/E Cycling Stress Effect 28
3.4 Summary 29

Chapter 4 Reliability Mechanisms of Data Retention and Read-Disturb in Nbit Flash Memory Cells 44
4.1 Introduction 44
4.2 Room-Temperature Threshold Voltage Drift 44
4.3 Read-Disturb Effects in Erase State 46
4.3.1 Commonality between Vt Drift and Read-Disturb 47
4.3.2 Gate and Drain Bias Dependences on Read-Disturb Behavior 47
4.4 Program-state Charge Loss 48
4.5 Summary 49

Chapter 5 Numerical Simulation of Program-State Charge Retention in SONOS Flash Memory Cell 61
5.1 Introduction 61
5.2 Retention Loss Simulation Model 62
5.2.1 Nitride Charge Dynamics and Loss Mechanisms 62
5.2.2 Assumptions in Simulation 66
5.3 Numerical Simulation Method 67
5.3.1 Explicit and Implicit Methods 67
5.3.2 Non-linear and Stiff System 68
5.3.3 Jacobian Matrix 69
5.3.4 Simulation Flowchart 71
5.4 Results and Discussion 72
5.4.1 Bottom Oxide Blocking Effect 72
5.4.2 Post-Stress Two-Stage Retention Loss 73
5.4.3 Leakage Component Separation 75
5.5 Summary 76

Chapter 6 Extraction of Nitride Trap Density from Stress Induced Leakage Current in SONOS Flash Memory 94
6.1 Introduction 94
6.2 Nitride Trap Characterization Technique 95
6.3 Summary 98

Chapter 7 Read Current Instability Arising from Random Telegraph Noise in Localized Storage, Multi-Level SONOS Flash Memory 105
7.1 Introduction 105
7.2 Experimental Setup 106
7.3 Two-region model 106
7.4 Results and Discussions 108
7.5 Summary 110

Chapter8 Conclusions 121

References 124
Vita 137
Publication Lists 138
Chapter 1
[1.1] R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, “Introduction to Flash memories,” Proc. IEEE, vol. 91, pp. 489-502, 2003
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[1.3] J. D. Lee, S. -H. Hur, and J. –D. Choi, “Effects of the floating-gate interferences on NAND Flash memory cell operation,” IEEE Elec. Dev. Lett., vol. 23, pp. 264-267, 2003
[1.4] H. Maes and J. F. Van Houdt, “Silicon scaling and its consequences for memory technology,” Proc. IEEE NVSM., pp. 7-9, 2003
[1.5] D. Kahng and S. M. Sze, “A Floating Gate and Its Application to Memory Devices,” Bell Syst. Tech. J., pp. 1283-1288, 1967
[1.6] Sam Pan, C. C. Yeh, Rich Liu, and C. Y. Lu, “Nonvolatile Memory Challenges toward Gigabit and Nano-scale Era and a Nan-scale Flash Cell: PHINES”, Solid State Devices and Materials, pp. 152-153, 2002
[1.7] T. Sugizaki, M. Kobayashi, M. Ishidao, H. Minakata, M. Yamaguchi, Y. Tamura, Y. Sugiyama, T. Nakanishi, and H. Tanaka, “Novel Multi-bit SONOS Type Flash Memory Using a High-k Charge Trapping Layer,” VLSI Tech. Dig., pp. 27-28, 2003
[1.8] C. H. Lai, Albert Chin, K. C. Chiang, W. J. Yoo, C. F. Cheng, S. P. McAlister, C. C. Chi and P. Wu, “Novel SiO2/AlN/HfAlO/IrO2 Memory with Fast Erase, Large �幀th and Good Retention,” VLSI Tech. Dig., pp. 210-211, 2005
[1.9] Jan Van Houdt, “HIGH-K MATERIALS FOR NONVOLATILE MEMORY APPLICATIONS,” Proc. Int. Reliab. Phys. Symp., pp. 234-239, 2005
[1.10] R. van Schaijk, M. van Duuren, N. Akil, A. Huerta, S. Beckx, F. Neuilly, Z. Rittersma, M. Slotboom, S. Van Elshocht and J. Wouters, “A Novel SONOS Memory with HfSiON/Si3N4/HfSiON Stack for Improved Retention,” Proc. IEEE NVSM., pp. 50-51, 2006
[1.11] H. C. Pao and O’Connell, “Memory Behavior of an MNS Capacitor,” Appl. Phys. Lett., vol. 12, pp. 260-262, 1968
[1.12] H. A. R. Wegener, A. J. Lincoln, H. C. Pao, M. R. O’Connel, and R. E. Oleksiak, “The Variable Threshold Transistor, A New Electrically-Alterable, Non-destructive Read-only Storage Device,” IEDM Tech. Dig., pp. 420-423, 1967
[1.13] Mehran Aminzadeh, Shinji Nozaki, R. V. Giridhar, “Conduction and charge trapping in polysilicon-silicon nitride-oxide-silicon structures under positive gate bias,” IEEE Trans. on Elec. Dev., vol. 35, pp. 459-467, 1988
[1.14] James A. Topich, “Long-term retention of SNOS nonvolatile memory devices,” IEEE Trans. on Elec. Dev., vol. 31, pp. 1908-1910, 1984
[1.15] Y. –N. Tan, Wai-Kin Chim, B. J. Cho, and Wee-Kiong Choi, “Over-erase phenomenon in SONOS-type flash memory and its minimization using a hafnium oxide charge storage layer,” IEEE Trans. on Elec. Dev., vol. 51, pp. 1143-1147, 1984
[1.16] Myung Kwan Cho, and Dae M. Kim, “High performance SONOS memory cells free of drain turn-on and over-erase: Compatibility issue with current flash technology,” IEEE Elec. Dev. Lett., vol. 21, pp. 399-401, 2000
[1.17] F. R. Libsch, A. Roy, and M. H. White, “Charge transport and storage of low programming voltage SONOS/MONOS memory devices,” Sol. State Elec., vol. 33, pp. 105-109, 1990
[1.18] T. K. Chan, K.K. Young, and C. Hu, “A True Single-transistor Oxide-Nitride-Oxide EEPROM Device”, IEEE Elec. Dev. Lett., Vol.8, pp. 93-95, 1987
[1.19] B. Eitan, P. Pavan, I.Bloom, E. Aloni, A. Frommer, and D. Finzi, “ NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell”, IEEE Electron Dev. Lett., Vol.21., No. 11, pp. 543-545, 2000
[1.20] W.J. Tsai, N.K. Zous, C.J. Liu, C.C. Liu, C.H. Chen, Tahui Wang, Sam Pan, and Chih-Yuan Lu, “Data Retention Behavior of a SONOS Type Two-Bit Storage Flash Memory Cell”, IEDM Tech. Dig., pp. 719-722, 2001
[1.21] Tahui Wang, W. J. Tsai, S. H. Gu, C. T. Chan, C. C. Yeh, N. K. Zous, T C. Lu, Sam Pan, and Chih-Yuan Lu, “Reliability Models of Data Retention and Read-Disturb in 2-bit Nitride Storage Flash Memory Cells (Invited Paper),” IEDM Tech. Dig., pp. 169-172, 2003
[1.22] H. T. Lue, T. H. Hsu, M. T. Wu, K. Y. Hsueh, Rich Liu, and Chih-Yuan Lu, “Studies of the cReverse Read Method and Second-Bit Effect of 2-Bit/Cell Nitride-Trapping Device by Quasi-Two-Dimensional Model,” IEEE Trans. on Elec. Dev., vol. 53, pp. 119-125, 2006
[1.23] W. P. Lu and S. H. Gu, “A Novel Hole Annealing Method,” patent pending, Taiwan, Republic of China, 2005
[1.24] Yakov Roizin, Evgeny Pikhay, and Micha Gutman, “Suppression of Erased State Vt Drift in Two-Bit Per Cell SONOS Memories,” IEEE Elec. Dev. Lett., vol. 26, pp. 35-37, 2005
[1.25] Takashi Hori and Takatoshi Yasui, and Susumu Akamatsu, “Hot-Carrier Effects in MOSFET’s with Nitrided-Oixde Gate-Dielectrics Prepared by Rapid Thermal Processing,” IEEE Trans. on Elec. Dev., vol. 39, pp. 134-147, 1992
[1.26] Jiankang Bu and Marvin H. White, “Improvement in retention reliability of SONOS nonvolatile memory devices by two-step high temperature deuterium anneals,” Proc. Int. Reliab. Phys. Symp., pp. 52-56, 2001
[1.27] Kuo-Hong Wu, Hua-Ching Chien, Chih-Chiang Chan, Tung-Sheng Chen, and Chin-Hsing Kao, “ SONOS device with tapered bandgap nitride layer,”IEEE Trans. on Elec. Dev., vol. 52, pp. 987-992, 2005
[1.28] Yu Wang and M. H. White, “An Analytical retention Model for SONOS Nonvolatile Memory Devices in the Excess Electron State,” Semiconductor Dev. Research Sym., pp. 157-157, 2003
[1.29] S. H. Gu, Tahui Wang, Wen-Pin Lu, Yen-Hui Joseph Ku, and Chih-Yuan Lu, “Numerical Simulation of Bottom Oxide Thickness Effect on Charge Retention in SONOS Flash Memory Cells with Fowler-Nordheim Programming,” IEEE Trans. on Elec. Dev., vol. 19, pp. 826-665, 2006
[1.30] S.H. Gu, C.W. Li, Tahui Wang, W.P. Lu, K.C. Chen, Joseph Ku, and Chih-Yuan Lu, “Read Current Instability Arising from Random Telegraph Noise in Localized Storage, Multi-Level SONOS Flash Memory,” accepted and to be published in IEEE International Electron Devices Meeting (IEDM), San Franciso, U.S.A., 2006

Chapter 2
[2.1] P. Cappelletti, C. Golla, P. Olivo, and E. Zanoni, “Flash MEMORIES,“ in KLUWER ACADEMIC, 2000
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[2.4] C. W. Tsai, S. H. Gu, L. P. Chiang, T. Wang, Y. C. Liu, L. S. Huang, M. C. Wang and L. C. Hsia, “Valence-Band Tunneling Enhanced Hot Carrier Degradation in Ultra-Thin Oxide nMOSFETs”, IEDM Tech. Dig., pp. 139-142, 2000
[2.5] Tahui Wang, Senior Member, IEEE, Lu-Ping Chiang, Nian-Kai Zous, Charng-Feng Hsu, Li-Yuan Huang, and Tien-Sheng Chao,“ A Comprehensive Study of Hot Carrier Stress-Induced Drain Leakage Current Degradation in Thin-Oxide n-MOSFET’s,” IEEE Trans. on Elec. Dev., vol. 46, pp. 1877-1882, 1999
[2.6] Tahui Wang, L. P. Chiang, T. E. Chang, N. K. Zous, K. Y. Shen, and C. Huang, “Reliability comparison of FLOTOX and textured polysilicon EEPROM’s,” Proc. Int. Reliability Phys. Symp., pp. 292-295, 1997
[2.7] E. F. Runnion, S. M., IV Gladstone, R. S. Scott, D. J. Dumin, L. Lie, and J. Mitros, “ Limitations on oxide thicknesses in flash EEPROM applications”, Proc. Int. Reliability Phys. Symp., pp. 93-99, 1996

Chapter 3
[3.1] Y. W. Chang, T. C. Lu, Sam Pan, and Chih-Yuan Lu, “Modeling for the 2nd-Bit Effect of a Nitride-Based Trapping Storage Flash EEPROM Cell Under Two-Bit Operation,” IEEE Elec. Dev. Lett., Vol. 25, pp. 95, 2004
[3.2] W. J. Tsai, N. K. Zous, M. H. Chou, Smile Huang, H. Y. Chen, Y. H. Yeh, M. Y. Liu, C. C. Yeh, T. Wang, Joseph Ku, and Chih-Yuan Lu, “Cause of Erase Speed Degradation during Two-Bit Per Cell Operation of A Trapping Nitride Storage Flash Memory Cell,” Proc. Int. Reliability Phys. Symp., pp. 522-526, 2004
[3.3] L. Larcher, G. Verzellesi, P. Pavan, E. Lusky, I. Bloom and B. Eitan, “Impact of Programming Charge Distribution on Threshold Voltage and Subthreshold Slope of NROM Memory Cells,” IEEE Trans. on Elec. Dev., pp.1939-1946, 2002
[3.4] S. H. Gu, M. T. Wang, C. T. Chan, N. K. Zous, C. C. Yeh, W. J. Tsai, T. C. Lu, Tahui Wang, Joseph Ku, and Chih-Yuan Lu, “Investigation of Programmed Charge Lateral Spread in a Two-bit Nitride Storage Flash Memory Cell by Using a Charge Pumping Technique,” Proc. Int. Reliability Phys. Symp., pp. 639-640, 2004
[3.5] S. H. Gu, Tahui Wang, W. P. Lu, Wenchi Ting, Y. Hui Joseph Ku, and Chih Yuan Lu, “Characterization of Programmed Charge Lateral Distribution in a Two-bit Storage Nitride Flash Memory Cell by Using a Charge Pumping Technique,” IEEE Trans. on Elec. Dev., vol. 53, pp. 103-108, 2006
[3.6] Chun Chen and T. P. Ma, “Direct Lateral Profiling of Hot-Carrier-Induced Oxide Charge and Interface Traps in Thin Gate MOSFET’s,” IEEE Trans. on Elec. Dev., vol. 45, pp.512-520, 1998
[3.7] W. Chen and T. P. Ma, “Oxide charge buildup and spread-out during channel-hot-carrier injection in N-MOSFET’s,” IEEE Elec. Dev. Lett., vol. 13, pp. 319-321, 1992
[3.8] M. G. ANCONA, N. S. SAKS, and D. Mccarthy, “Lateral Distribution of Hot-Carrier-Induced Interface Traps in MOSFET’s,” IEEE Trans. on Elec. Dev., vol. 35, pp. 2221-2228, 1988
[3.9] N. K. Zous, Y. J. Chen, C. Y. Chin, W. J. Tsai, T. C. Lu, M. S. Chen, W. P. Lu, T. Wang, Sam Pan, and C. Y. Lu, “An Endurance Evaluation Method for Flash EEPROM,” IEEE Trans. on Elec. Dev., vol. 51, pp. 720-725, 2004
[3.10] J. Wu, L. F. Register, and E. Rosenbaum, “Trap-Assisted Tunneling Current Through Ultra-Thin Oxide,” Proc. Int. Reliability Phys. Symp., pp. 389-395, 1999

Chapter 4
[4.1] Tahui Wang, W. J. Tsai, S. H. Gu, C. T. Chan, C. C. Yeh, N. K. Zous, T C. Lu, Sam Pan, and Chih-Yuan Lu, “Reliability Models of Data Retention and Read-Disturb in 2-bit Nitride Storage Flash Memory Cells (Invited Paper),” IEDM Tech. Dig., pp. 169-172, 2003
[4.2] B. Eitan, P. Pavan, I.Bloom, E. Aloni, A. Frommer, and D. Finzi, “ NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell”, IEEE Elec. Dev. Lett., vol.21., No. 11, pp. 543-545, 2000
[4.3] D. J. Dumin and J. Maddux, “Correlation of Stress-Induced Leakage Current in Thin Oxide with Trap Generation Inside the Oxide,” IEEE Trans. on Elec. Dev., vol. 40, pp986, 1993
[4.4] K. Lehovec and A. Fedotowsky, “A Charge retention of MNOS devices limited by Frenkel-Poole detrapping”, J. Appl. Phys., Vol. 32, pp. 335, 1978.
[4.5] B. Ricc��, G Gozzi, and M. Lanzoni, “ Modeling and Simulation of Stress-Induced Leakage Current in Ultrathin SiO2 Films,” IEEE Trans. on Elec. Dev., vol. 45, pp. 1554-1560, 1998.
[4.6] W. J. Tsai, N. K. Zous, C. J. Liu, C. C. Liu, C. H. Chen, Tahui Wang, Sam Pan and Chih-Yuan Lu, “Data Retention Behavior of a SONOS Type Two-Bit Storage Flash Memory Cell,” IEDM Tech. Dig., pp. 719-722, 2001.
[4.7] A. Roy and M. H. White, “ A New Approach to Study Electron and Hole Charge Separation at the Semiconductor-Insulator Interface,” IEEE Trans. on Elec. Dev., vol. 37, pp. 1504-1513, 1990
[4.8] W. J. Tsai, C. C. Yeh, N. K. Zous, C. C. Liu, S. K. Cho, Tahui Wang, Samuel C. Pan and Chin-Yuan Lu, “ Positive Oxide Charge-Enhanced Read Disturb in a Localized Trapping Storage Flash Memory Cell,” IEEE Trans. on Elec. Dev., vol. 51, pp. 434-439, 2004
[4.9] Tahui Wang, N. K. Zous, J. L. Lai and C. Huang, “Hot hole Stress Induced Leakage Current (SILC) Transient in Tunnel Oxides,” IEEE Elect. Dev. Lett., vol. 19, pp. 411-413, 1998.
[4.10] Taihu Wang, N. K. Zous, and C. C. Yeh, “Role of positive trapped charge in stress-induced leakage current for Flash EEPROM devices,” IEEE Trans. on Elec. Dev., pp.1910-1916, 2002
[4.11] S. Jeon, J. H. Han, J. Lee, S. Choi, H. Hwang, and Chungwoo Kim, “Impact of metal work function on memory properties of charge-trap flash memory devices using fowler-nordheim P/E mode,” IEEE, Elect. Dev. Lett., vol. 27, pp. 486-488, 2006

Chapter 5
[5.1] L. Lundkvist, I. Lundst�宁m, and C. Svensson,” Discharge of MNOS Structures,” Sol. State Elec., vol. 16, pp. 811-823, 1973.
[5.2] L. Lundkvist, C. Svensson, and B. Hansson,” Discharge of MNOS Structures at Elevated Temperatures,” Sol. State Elec., vol. 19, pp. 221-227, 1976.
[5.3] P. J. McWhorter, S. L. Miller, and T. A. Dellin, “Modeling the memory retention characteristics of silicon-nitride-oxide-silicon nonvolatile transistors in a varying thermal environment,” J. Appl. Phys., vol. 68, pp. 1902-1909, 1990.
[5.4] K. Lehovec and A. Fedotowsky, “Charge Retention of MNOS Devices Limited by Frenkel-Poole Detrapping”, Appl. Phys. Lett., vol. 32, pp. 335-338, 1978.
[5.5] Ross A. Williams and Moiz M. E. Beguwala, ”The Effect of Electrical Conduction of Si3N4 on the Discharge of MNOS Memory Transistors,” IEEE Trans. on Elec. Dev., vol. 25, pp.1019-1023, 1978.
[5.6] Y. Yang, M. H. White, “Charge Retention of Scaled SONOS Nonvolatile Memory Devices at Elevated Temperatures,” Sol. State Elec., vol. 44, pp. 948-958, 2000.
[5.7] Yu Wang and M. H. White, “An Analytical retention Model for SONOS Nonvolatile Memory Devices in the Excess Electron State,” Sol. State Elec., vol. 49, p.97, 2005.
[5.8] Gowrishankar L. Chindalore, C. T. Swift, and David Burnett, “A New Combination-Erase Technique for Erasing Nitride Based (SONOS) Nonvolatile Memories,” IEEE, Elect. Dev. Lett., vol. 24, p.257-259, 2003
[5.9] M. Specht, U. Dorda, L.Dreeskornfeld, J.Kretz, F. Hofmann, M.St�黌ele, R.J.Luyken, W.R�宄ner, H.Reisinger, E. Landgraf, T.Schulz, J.Hartwich, R. K�卌mling, L.Risch, “20 nm tri-gate SONOS memory cells with multi-level operation,” VLSI Tech. Dig., 2004
[5.10] V. A. Gritsenko, “Nonstationary Electrons and Holes Transport by Depolarization of MNOS Structures: Experiment and Numerical Simulation,” Microelectronics, vol. 16, pp.42-50. 1987
[5.11] W. Schockley and W. T. Read, Jr., “Statistics of the Recombinations of Holes and Electrons,” Phys. Rev., vol. 87, pp. 835-842, 1952.
[5.12] P. C. Arnett, “Transient conduction in insulators at high fields,” J. Appl. Phys., vol. 46, pp. 5236-5243, 1975
[5.13] Taihu Wang, N. K. Zous, and C. C. Yeh, “Role of positive trapped charge in stress-induced leakage current for Flash EEPROM devices,” IEEE Trans. on Elec. Dev., pp.1910-1916, 2002
[5.14] V. Vasudevan and J. Vasi, “A simulation of multiple trapping model for continuous time random walk transport,” J. Appl. Phys., vol. 74, pp. 3224-3230, 1993
[5.15] D. Debuf, “General theory of carrier lifetime in semiconductors with multiple localized states,” J. Appl. Phys., vol. 96, pp. 6454-6469, 2004
[5.16] K. A. Nasyrov, V. A. Gritsenko, M. K. Kim, H. S. Chae, S. D. Chae, W. I. Ryu, J. H. Sok, J.-W. Lee, and B. M. Kim, “Charge Transport Mechanism in Metal-Nitride-Oxide-Silicon Structures,” IEEE Elec. Dev. Lett., vol. 23, pp. 336-338, 2002
[5.17] B. De Salvo, G. Ghibaudo, G. Pananakakis, P. Masson, T. Baron, N. Buffet, A. Fernandes, and B. Guillaumot, “Experimental and theoretical investigation of nano-crystal and nitride-trap memory devices,” IEEE Trans. Elec. Dev., vol. 48, pp.1789-1799, 2001
[5.18] M. H. White, D. A. Adams, J. R. Murray, S. Wrazien, Yijie Zhao, Yu Wang, B. Khan, W. Miller, R. Mehrotra, “Characterization of scaled SONOS EEPROM memory devices for space and military systems,” Proc. IEEE NVSM., pp. 51-59, 2004
[5.19] S. Kamohara, D. Park, and C. Hu, “Deep-Trap SILC(Stress Induced Leakage Current) Model For Nominal and Weak Oxides,” Proc. Int. Reliability Phys. Symp., pp. 57-61, 1998
[5.20] T. K. Kang, M. J. Chen, C. H. Liu, Chang Y.J., and S. K. Fan, “Numerical confirmation of inelastic trap-assisted tunneling (ITAT) as SILC mechanism,” IEEE Trans. on Elec. Dev, vol. 48, pp.2317-2322, 2001
[5.21] M. Silver and L. Cohen, “Monte Carlo simulation of anomalous transit-time dispersion of amorphous solids,” Phys. Rev. B., vol. 15, pp. 3276-3278, 1977.
[5.22] C. Main, S. Reynolds, and R. Br�伳gemann, “Decay from steady-state photocurrent in amorphous semiconductors,” Phys.stat. sol.(c), vol. 5, pp. 1194-1207, 2004
[5.23] S. H. Gu, Tahui Wang, C. W. Hsu, W. P. Lu, Y. Hui Joseph Ku, and Chih Yuan Lu, “Numerical Simulation of Bottom Oxide Thickness Effect on Charge Retention in SONOS Flash Memory Cells with Fowler-Nordheim Programming,” to be accepted in IEEE Trans. on Elec. Dev. (TED), 2007
[5.24] Curtis F. Gerald, “Applied Numerical Analysis Second Efition,” in Addison-Wesley, 1977
[5.25] T. R. Oldham, A. J. Lelis, and F. B. Mclean, “Spatial dependence of trapped holes determined from tunneling analysis and measured annealing,” IEEE Trans. Nucl. Dev., vol. 40, pp. 1203-1207, 1986
[5.26] Tahui Wang, W. J. Tsai, S. H. Gu, C. T. Chan, C. C. Yeh, N. K. Zous, T. C. Lu, Sam Pan and C. Y. Lu, “Reliability Models of Data Retention and Read-Disturb in 2-bit Nitride Storage Flash Memory Cells,” IEDM Tech. Dig., pp. 169-172, 2003
[5.27] K. I. Lundstr�卌, and C. M. Svensson, “Properties of MNOS structures,” IEEE Trans. Elec. Dev., Vol. 19, pp.826-836, 1972.

Chapter 6
[6.1] K. I. Lundstr�卌, and C. M. Svensson, “A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors,” IEEE Trans. on Elec. Dev., vol. 19, pp. 826-665, 1972
[6.2] R. E. Paulsen, R. R. Siergiej, M. L. French, and M. H. White, “A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors,” IEEE Elec. Dev. Lett., vol. 13, pp. 627-338, 1992
[6.3] Y. Yang, M. H. White, “Charge Retention of Scaled SONOS Nonvolatile Memory Devices at Elevated Temperatures,” Sol. State Elec., vol. 44, pp. 948-958, 2000
[6.4] Yu Wang and M. H. White, “An Analytical retention Model for SONOS Nonvolatile Memory Devices in the Excess Electron State,” Sol. State Elec., vol. 49, p.97, 2005
[6.5] S. H. Gu, Tahui Wang, Wen-Pin Lu, Yen-Hui Joseph Ku, and Chih-Yuan Lu, “Extraction of Nitride Trap Density from Stress Induced Leakage Current in Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) Flash Memory,” Appl. Phys. Lett., vol. 12, pp. 260-262, 1968

Chapter 7
[7.1] K. C. Smith, “The prospects for multivalued logic: a technology and application view, ” IEEE Trans. Computers, vol. C-30, pp. 619-634, 1981.
[7.2] M. Horiguchi, M. Aoki, Y. Nakagome, S. Ikenaga, and K. Shimohigashi, “An experimental large-capacity semiconductor file memory using 16-level/cell storage,” IEEE J. Solid-State Circuits, vol. SC-23, pp. 27-33, 1988.
[7.3] E. Harari, “Flash EEPROM memory system having multi-level storage cells,” U.S. Patent #5,043,940, 1991.
[7.4] B. Eitan, “4-bit per cell NROM reliability,” IEDM Tech. Dig., pp. 539-542, 2005.
[7.5] Y. Polansky, A. Lavan, R. Sahar, O. Dadashev, Y. Betser, G. Cohen, E. Maayan, B. Eitan, T. C. T. Chen, C. H. Chang, C. Y. Liao, C. K. Chen, W. C. Ho, Y. S., W. P. Lu, W. C. Ting, F. L. Ni, Y. H. Joseph Ku, Chih-Yuan Lu, “A 4 bits per cell NROM 1Gb Data Storage Memory,” ISSCC Dig. Tech., pp. 34-38, 2006
[7.6] K. S. Ralls, W. J. Skocpol, L. D. Jackel, R. E. Howard, L. A. Fetter, R. W. Epworth, and D. M. Tennant, “Discrete resistance switching in submicron silicon inversion layers: individual interface traps and low frequency (1/f?) noise,” Phys. Rev. Lett., vol. 52, pp. 228-, 1984
[7.7] M. J. Kirton and M. J. Uren, “Noise in solid state microstructure: a new perspective on individual defects, interface states, and low-frequency (1/f) noise,” Adv. in Phys., vol. 38, pp. 367-468, 1989.
[7.8] H. Kurata, “20 nm tri-gate SONOS memory cells with multi-level operation,” VLSI Tech. Dig., 2006
[7.9] S. H. Gu, C. W. Li, Tahui Wang, W. P. Lu, K. C. Chen, Y. Hui Joseph Ku, and Chih Yuan Lu, “Read Current Instability Arising from Random Telegraph Noise in Localized Storage, Multi-Level SONOS Flash Memory,” to be published in IEEE International Electron Devices Meeting (IEDM), San Franciso, U.S.A., 2006
[7.10] M. H. Tsai and T. P. Ma, “The Impact of Device Scaling on the Current Fluctuations in MOSFET’s,” IEEE Trans. on Elec. Dev., vol. 41, pp. 2061-2068, 1994
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