臺灣博碩士論文加值系統

這篇論文是考慮在正交多頻分工(OFDM)系統中所傳送信號有著令人討厭的高峰均功率比的問題。在多輸入輸出正交多頻分工( MIMO-OFDM)系統中，因為多根傳送天線，處理峰均功率比的低複雜度架構是很重要的。在眾多降低峰均功率比的方法中，選擇對應法( SLM )是有著相對較高的降低峰均功率比的能力，但同時也有著較高的複雜度和需要傳送額外訊息的缺點。這篇論文中，結合了低複雜度的SLM和傳送額外訊息，模擬顯示他能有效地降低峰均功率比。並將使用多輸入輸出正交分頻多工系統的802.11n規格實作在DSP板上，數據表示出在系統中這架構的確有著很低的時間複雜度。

This thesis considers the Orthogonal Frequency Division Multiplexing (OFDM) system’s undesirable feature of a large peak-to-average power ratio (PAPR) of the transmitted signal. In the MIMO-OFDM system, a low complexity structure to deal with PAPR problem is important because multiple transmitter. In the various PAPR reduction methods, the method selected mapping has high PAPR reduction capability but also high complexity and needs to transmit additional side information. In this thesis, we combine low complexity SLM structure and transmitting the side information, simulation display this method can reduce PAPR effectively. And implement to DSP board using 802.11n which is MIMO-OFDM system, profiling that this structure has low complexity and doesn’t engage much time in the system.

Chapter 1 Introduction...........................9
1.1 PAPR Reduction Scheme........................11
1.1.1 Direct clipping............................11
1.1.2 Block coding...............................11
1.1.3 Partial Transmit Sequence (PTS)............12
1.1.3 Selected Mapping (SLM).....................14
1.1.4 tone injection (TI)........................15
1.1.5 Tone reservation (TR)......................16
1.2 A Low Complexity SLM with conversion matrix[13]................17
Chapter 2 The Brief of EWC PHY Specification For 802.11n.............20
2.1 PLCP Packet Format...........................20
2.2 Operating Mode...............................21
2.3 Modulation and Coding Scheme(MCS)............22
2.4 Transmitter Block Diagram....................25
2.5 Timing Parameter.............................26
Chapter 3 The Brief of Innovative Quixote DSP Board......28
3.1 About Quixote............................28
3.2 Support libraries........................29
Chapter 4 Developing A DSP Program...........32
4.1 A recommended flow of developing a DSP program....32
4.2 Analyzing the C code performance.........33
4.3 Refine the C/C++ code....................34
4.3.1 Using the intrinsic to replace complicated C/C++ code...34
4.3.2 Loop Unrolling.........................35
4.3.2 Word access to the packed data.........36
4.3.2 Using compiler option..................36
4.3 Write linear assembly code...............37
Chapter 5 DSP Board Implementation Result and Discussion....39
5.1 Choose M = 4 in SLM structure.............39
5.2 The use of the conversion matrix..........40
5.3 About insert the side information.........41
5.3 Fixed point format on the DSP board.......42
5.3 Code performance on the DSP board.........43
5.4 About using the digital IO................44
5.5 The estimate of speeding up the program using FPGA....................46
Chapter 6 Conclusion..........................49
Chapter 7 Reference...........................50

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”[14]Innovative Quixote user manual