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研究生:涂峻豪
研究生(外文):Chun-Hao Tu
論文名稱:新穎低溫複晶矽薄膜電晶體與前瞻非揮發性記憶體元件之製作與特性研究
論文名稱(外文):Fabrication and Characterization of Novel Low Temperature Polycrystalline Silicon Thin-Film Transistors and Advanced Nonvolatile Memory
指導教授:張俊彥 / 張鼎張
指導教授(外文):Chun-Yen Chang / Ting-Chang Chang
學位類別:博士
校院名稱:國立交通大學
系所名稱:電子工程系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:中文
論文頁數:169
中文關鍵詞:複晶矽薄膜電晶體非揮發性記憶體
外文關鍵詞:Poly-Si TFTsNonvolatile Memory
相關次數:
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  • 下載下載:74
  • 收藏至我的研究室書目清單書目收藏:1
本論文首先提出以鈍化方式來提昇低溫複晶矽薄膜電晶體(Poly-Si TFTs)的特性以及元件的可靠度。本論文提出在非晶矽薄膜沈積後,以氟(F)離子佈植的方式,先預先植入非晶矽薄膜中,其佈植劑量為5×1013cm-2。經過傳統的固態結晶技術(SPC)之後,再進行後續的元件製作。我們發現經過氟離子佈植過後的複晶矽薄膜電晶體其元件特性相較於傳統的固態結晶的薄膜電晶體,有比較低的起始電壓(VTH),較低的次臨界導通特性(S.S),以及較高的載子移動率(μFE)。此乃由於氟離子佈植會降低複晶矽薄膜中本身的缺陷(trap),包括淺能階(tail state)以及深能階(deep state)的缺陷,進而提昇元件的特性。相較於傳統的氟離子佈植的鈍化方法,在做熱結晶前並沒有額外的氧化層沈積。經過固態熱結晶後,薄膜中的氟離子會聚積到複晶矽的表面,以及複晶矽與緩衝氧化層(buffer oxide)的介面,此乃氟離子會受熱而往氧化層聚積。複晶矽表面的原生氧化層(native oxide)同時也具有使氟離子聚積的驅動力。這不但可以將傳統以氟離子佈植來鈍化複晶矽薄膜電晶體的技術的製程步驟減少,以及減少元件製程的複雜度。更進一步地討論,當氟離子佈植劑量提高到5×1015cm-2時,元件的特性卻造成劣化,此乃因為過多的佈植劑量將無法完全溶解在複晶矽薄膜中,形成額外的缺陷,卻降低了低溫複晶矽薄膜電晶體的特性。其經過氟離子佈植後而進行固態熱結晶的複晶矽晶粒尺寸也在此被討論,我們發現複晶矽晶粒大小並沒有隨著佈植劑量有改變。因此,其元件特性的提昇乃是由於氟離子的鈍化造成的結果。
同樣地,我們也發現以準分子雷射(excimer laser)進行雷射結晶的低溫複晶矽薄膜電晶體,也與傳統的固態結晶方法結晶的技術有相似的結果。由於雷射結晶是個快速的製程步驟,複晶矽薄膜以及緩衝氧化層也因快速的熱膨脹造成額外的缺陷密度。往複晶矽與緩衝氧化層介面聚積的氟離子將可以消除雷射結晶所造成額外的缺陷密度。我們也發現過高的氟離子佈植劑量也會造成元件特性的劣化。此乃由於複晶矽薄膜本身對氟離子的固態溶解度的問題。同時,我們發現以氟離子佈植劑量為5×1013cm-2時,複晶矽晶粒比起傳統以及高劑量的複晶矽晶粒要來的大。因此,元件特性的提昇乃因為晶粒尺寸提昇以及氟離子鈍化的結果。
我們同時也對經氟離子佈植的低溫複晶矽薄膜電晶體元件做可靠度的探討。我們發現經過氟離子佈植過後的元件具有較高的直流(DC)偏壓下的電性可靠度,包括較低的起始電壓的漂移、次臨界特性漂移、以及導通電流漂移。此乃因為佈植的矽-氟(Si-F)鍵取代矽-矽(Si-Si)以及矽-氫(Si-H),使得較強鍵結的矽-氟鍵可以抵抗電流的衝擊,造成可靠度的提昇。更進一步地討論,我們也發現氟離子佈植劑量為5×1013cm-2¬的時候,其載子移動率可以提昇到兩倍。而氟離子佈植應用在準分子雷射結晶的元件上,具有較為明顯的可靠度提昇。此乃因為以雷射結晶的元件具有較低的薄膜缺陷密度,使得後續的電流衝擊也不致破壞元件的可靠度。事實上,也發現矽-氟鍵的強鍵結可以抵抗由於準分子雷射結晶造成較高的載子移動率,造成較低的劣化程度。因此,氟離子佈植在結晶前的應用技術,更適用在以雷射結晶的方法。
以新結構方式來提高低溫複晶矽薄膜電晶體元件的可靠度,在此論文也提出來討論。我們提出以具氟摻雜的氧化矽(F-incorporated SiOx,FSG)作為新穎的側壁子(spacer)材料。側壁子結構可以降低元件在汲極端的高電場,可以降低載子得到高的撞擊能量而造成斷鍵。具氟摻雜的氧化矽在複晶矽的表面產生保護的作用,相較於傳統以氧化矽為側壁子材料的低溫複晶矽薄膜電晶體具有壓抑的扭結效應(kink effect),以及較明顯的可靠度提昇。
本論文同時也針對非揮發性記憶體元件做研究。我們提出兩種氮化矽鍺的堆疊結構氮化矽鍺(SiGeN)作為鍺奈米點(Ge nanocrystal)的自我析出層(self-assembling layer),其一為以厚的氮化矽鍺作為自我析出層;其二為在氮化矽鍺沈積後,隨即成長非晶矽薄膜(a-Si)。經過高溫熱氧化後,鍺奈米點會自我析出在氮氧化矽(SiON)薄膜中。厚的氮化矽鍺薄膜堆疊結構以長時間的熱氧化來析出鍺奈米點,隨即形成較厚的氮氧化矽作為阻擋氧化層;而具非晶矽薄膜的堆疊結構以短時間的熱氧化來析出鍺奈米點,隨即再經由高溫水氣處理後,提昇阻擋氧化層自身的品質,可以抵抗儲存的電荷流失至閘極金屬。其明顯的記憶視窗(memory window)是來自於鍺奈米點的貢獻。
我們也針對傳統的氮氧化矽作為載子儲存層的堆疊結構,以及矽鍺薄膜作為鍺奈米點自我析出層的結構做比較。我們發現本論文所提出的鍺奈米點埋在氮氧化矽的結構,其得到的記憶體效應比傳統的氮氧化矽薄膜,以及鍺奈米點埋在氧化層中的堆疊結構還大。甚至其記憶體效應比兩者的疊加結果還要大,此乃因為鍺奈米點埋在氮氧化矽為主的載子儲存層中,會產生額外的儲存中心,進而增進記憶體效能。
Chinese Abstract------------------------------------------------------- I
English Abstract-------------------------------------------------------------- III
Acknowledgement ------------------------------------------------------------VI
Content ----------------------------------------------------------------------- -VIII
Table Captions-----------------------------------------------------------------XI
Figure Captions -- XII
Chapter 1 Introduction
1.1 Overview of Poly-silicon Thin-Film Transistor Technology ----------- 1
1.1.1 Defects in Poly-Si Film ----------------------------------------------- 3
1.1.2 Motivation -------------------------------------------------------------- 4
1.2 Overview of Nonvolatile Memory------------------------------------------ 6
1.2.1 SONOS nonvolatile memory devices ------------------------------- 7
1.2.2 Nanocrystal nonvolatile memory devices -------------------------- 8
1.2.3 Motivation -------------------------------------------------------------- 9
1.3 Thesis Organization --------------------------------------------------------- 11

Chapter 2 Poly-Si TFTs Conduction Mechanism and Nonvolatile Memory Basics Principles
2.1 Poly-Si TFTs Transportation Mechanisms------------------------- 14
2.1.1 Methods of Device Parameter Extraction 17
2.1.2 Poly-Si TFTs Non-Ideal Effect 22
2.2 Nonvolatile Memory Basics Principle 23
2.2.1 Programming/Erasing Mechanism 23
2.2.2 Nonvolatile Memory Reliability 29
2.2.3 Nanocrystal Memory 32
Chapter 3 Enhancement of Fluorine-Ions-Implanted Poly-Si Thin Film Transistors using Solid Phase Crystallization
3.1 Introduction 45
3.2 Experimental 46
3.3 Results and discussion 47
3.4 Conclusions 50


Chapter 4 Performance Enhancement of Excimer Laser Crystallized Poly-Si Thin Film Transistors with Fluorine Implantation Technology
4.1 Introduction 57
4.2 Experimental 58
4.3 Results and discussion 59
4.4 Conclusions 62

Chapter 5 Improved Performance of F-Ions-Implanted Poly-Si Thin Film Transistors using Solid Phase Crystallization and Excimer Laser Crystallization
5.1 Introduction 69
5.2 Experimental 71
5.3 Results and discussion 71
5.4 Conclusions 75

Chapter 6 Improvement of Reliability for Polycrystalline Thin Film Transistors Using Self-aligned Fluorinated Silica Glass (FSG) Spacers
6.1 Introduction 82
6.2 Experimental 83
6.3 Results and discussion 84
6.4 Conclusions 86

Chapter 7 Formation of Germanium Nanocrystals Embedded in Silicon-Oxygen-Nitride Layer
7.1 Introduction 91
7.2 Experimental 92
7.3 Results and discussion 93
7.4 Conclusions 96

Chapter 8 Improved Memory Window for Ge Nanocrystals Embedded in SiON Layer
8.1 Introduction 105
8.2 Experimental 106
8.3 Results and discussion 107
8.4 Conclusions 108

Chapter 9 Applications of Thermal Treatment for Germanium Nanocrystal Embedded in Silicon-Oxygen-Nitride Layer
9.1 Introduction 115
9.2 Experimental 116
9.3 Results and discussion 116
9.4 Conclusions 120

Chapter 10 Applications of Thermal Treatment for Silicon Germanium Nitride (SiGeN) Layer on Nonvolatile Memory
10.1 Introduction 131
10.2 Experimental 131
10.3 Results and discussion 132
10.4 Conclusions 135

Chapter 11 Conclusions Remarks 147

Chapter 12 Future Work 150

References 151
Vitae 165
Publication List 166
Chapter 1
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Chapter 2
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Chapter 3
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[3.8] I. W. Wu, A. G. Lewis, T. Y. Huang, A. Chiang, “Effects of trap state density reduction by plasma hydrogenation in low-temperature polysilicon TFT,” IEEE Electron Device Letters., vol. 10, pp. 123–125, 1989
[3.9] H. N. Chern, C. L. Lee, T. F. Lei, “The effects of fluorine passivation on polysilicon thin-film transistors,” IEEE Trans. Electron Devices., vol. 41, pp. 698-702, 1994
[3.10] J. W. Park, B. T. Ahn, K. Lee, “Effects of F+ Implantation on the Characteristics of Poly-Si Films and Low-Temperature n-ch Poly-Si Thin-Film Transistors,” Japan Journal of Applied Physics., vol. 34, pp. 1436-1441, 1995
[3.11] C. L. Fan, M. C Chen, “Performance Improvement of Excimer Laser Annealed Poly-Si TFTs Using Fluorine Ion Implantation,” Electrochemical and Solid-State Letters., vol. 5, pp. G75-G77, 2002
[3.12] S. Banerjee, R. Sundaresan, H. Shichijo, S. Malhi, “Hot-electron degradation of n-channel polysilicon MOSFETs,” IEEE Transaction on Electron Devices., vol. 35, pp. 152-157, 1988
[3.13] M. Hack, A. G. Lewis, I. W. Wu, “Physical models for degradation effects in polysilicon thin-film transistors,” IEEE Transaction on Electron Devices., vol. 40, pp. 890-897, 1993
[3.14] Sands T, Ishburn J, Myers E, Sadana D K, Nucl. Instrum. Methods., B 7/8, 337, 1985
[3.15] Galloni R, Rizzoli R, Nylandsted-Larsen A, Shiryaev S Yu, Nucl. Instrum. Methods B 19/20, 466, 1987

Chapter 4
[4.1] T. Sameshima, S. Usui, M. Sekiya, “XeCl excimer laser annealing used in the fabrication of poly-Si TFTs,” IEEE Electron Device Letters., vol. 7, pp. 276–278, 1986
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[4.4] D. Kouvatsos, J. G. Huang, R. J. Jaccodine, “Fluorine-Enhanced Oxidation of Silicon,” Journal of Electrochemical Society., vol. 138, pp. 1752-1755, 1991
[4.5] T. Kuan, A. Chou, J. Kanicki, “Two-dimensional numerical simulation of solid-phase-crystallized polysilicon thin-film transistor characteristics,” Japan Journal of Applied Physics., Part 1, vol. 38, pp. 2251-2255, 1999
[4.6] I. W. Wu, A. G. Lewis, T. Y. Huang, A. Chiang, “Effects of trapstate density reduction by plasma hydrogenation in low-temperature polysilicon TFT,” IEEE Electron Device Letters., vol. 10, pp. 123–125, 1989
[4.7] H. N. Chern, C. L. Lee, T. F. Lei, “The effects of fluorine passivation on polysilicon thin-film transistors,” IEEE Transaction on Electron Devices., vol. 41, pp. 698-702, 1994
[4.8] J. W. Park, B. T. Ahn, K. Lee, “Effects of F+ Implantation on the Characteristics of Poly-Si Films and Low-Temperature n-ch Poly-Si Thin-Film Transistors, ” Japan Journal of Applied Physics., vol. 34, pp. 1436-1441, 1995
[4.9]. C. H. Tu, T. C. Chang, P. T. Liu, H. W. Zan, Y. H. Tai, C. Y. Yang, Y. C. Wu, H. C. Liu, W. R. Chen, C. Y. Chang, “Enhanced Performance of Poly-Si Thin Film Transistors Using Fluorine Ions Implantation,” Electrochemical and Solid-State Letters., vol. 8, pp. G246-G248, 2005
[4.10] C. H. Tu, T. C. Chang, P. T. Liu, C. Y. Yang, H. C. Liu, W. R. Chen, Y. C. Wu, C. Y. Chang, “Improvement of electrical characteristics for fluorine-ion-implanted poly-Si TFTs using ELC,” IEEE Electron Device Letters., vol. 27, pp. 262-264, 2006
[4.11] C. L. Fan, M. C Chen, “Performance Improvement of Excimer Laser Annealed Poly-Si TFTs Using Fluorine Ion Implantation,” Electrochemical and Solid-State Letters., vol. 5, pp. G75-G77, 2002
[4.12] Fortunato G, Migliorato P, “Determination of gap. state density in polycrystalline silicon by field-effect conductance,” Applied Physics Letters., vol. 49, pp. 1025-1027, 1986
[4.13] S.Banerjee, R. Sundaresan, H. Shichijo, S. Malhi, “Hot-electron degradation of n-channel polysilicon MOSFETs,” IEEE Transaction on Electron Devices., vol. 35, pp. 152-157, 1988
[4.14] M. Hack, A. G. Lewis, I. W. Wu, “Physical models for degradation effects in polysilicon thin-film transistors,” IEEE Transaction on Electron Devices., vol. 40, pp. 890-897, 1993
[4.15] Sands T, Ishburn J, Myers E, Sadana D K, Nucl. Instrum. Methods., B 7/8, 337, 1985
[4.16] Galloni R, Rizzoli R, Nylandsted-Larsen A, Shiryaev S Yu, Nucl. Instrum. Methods B 19/20, 466, 1987
[4.17] Carlsson J-O, Boman M, “Selective deposition of tungsten—prediction of selectivity,” Journal of Vacuum Science & Technology A ., vol. 3, pp. 2298-2302, 1985

Chapter 5
[5.1] R.E.I. Schropp, B. Stannowski, J.K. Rath, “New challenges in thin film transistor (TFT) research,” Journal of Non-Crystalline Solids, vol. 299–302, pp. 1304–1310, 2002
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[5.3] J. S. Im, R. S. Sposili, M. A. Crowder, “Single-crystal Si films for thin-film transistor devices,” Applied Physics Letters., vol. 70, no. 25, pp. 3434–3436, 1997
[5.4] I. W. Wu, A. G. Lewis, T. Y. Huang, A.Chiang, “Passivation kinetics of two types of defects in polysilicon TFT by plasma hydrogenation,” IEEE Electron Device Letters., vol. 12, pp. 181-183, 1993
[5.5] H. N. Chern, C. L. Lee, T. F. Lei, “The effects of fluorine passivation on polysilicon thin-film transistors,” IEEE Trans. Electron Devices., vol. 41, pp. 698-702, 1994
[5.6] J. W. Park, B. T. Ahn, K. Lee, “Effects of F+ Implantation on the Characteristics of Poly-Si Films and Low-Temperature n-ch Poly-Si Thin-Film Transistors, ” Japan. Journal of Applied Physics., vol. 34, pp. 1436-1441, 1995
[5.7] C. H. Tu, T. C. Chang, P. T. Liu, H. W. Zan, Y. H. Tai, C. Y. Yang, Y. C. Wu, H. C. Liu, W. R. Chen, C. Y. Chang, “Enhanced Performance of Poly-Si Thin Film Transistors Using Fluorine Ions Implantation,” Electrochemical and Solid-State Letters.,vol. 8, pp. G246-G248, 2005
[5.8] C. H. Tu, T. C. Chang, P. T. Liu, C. Y. Yang, H. C. Liu, W. R. Chen, Y. C. Wu, C. Y. Chang, “Improvement of Electrical Characteristics for Fluorine-Ion-Implanted Poly-Si TFTs Using ELC,” IEEE Electron Device Letters, vol. 27, pp. 262-264, 2006
[5.9] T. Kuan, A. Chou, J. Kanicki, “Two-Dimensional Numerical Simulation of Solid-Phase-Crystallized Polysilicon Thin-Film Transistor Characteristics,” Japan Journal of Applied Physics., Part 1, vol. 38, pp. 2251-2255, 1999
[5.10] C. L. Fan, M. C Chen, “Performance Improvement of Excimer Laser Annealed Poly-Si TFTs Using Fluorine Ion Implantation,” Electrochemical and Solid-State Letters., vol. 5, pp. G75-G77, 2002
[5.11] Fortunato G, Migliorato P, “Determination of Gap State Density in Polycrystalline Silicon by Field- Effect Conductance,” Applied Physics Letters., vol. 49, pp. 1025-1027, 1986
[5.12] S. Banerjee, R. Sundaresan, H. Shichijo, S. Malhi, “Hot-electron degradation of n-channel polysilicon MOSFETs,” IEEE Transaction on Electron Devices., vol. 35, pp. 152-157, 1988
[5.13] M. Hack, A. G. Lewis, I. W. Wu, “Physical models for degradation effects in polysilicon thin-film transistors,” IEEE Transaction on Electron Devices., vol. 40, pp. 890-897, 1993

Chapter 6
[6.1] H. Oshima, S. Morozumi, “Future trends for TFT integrated circuits on glass substrates,” IEDM Tech. Dig., pp. 157-160, 1989
[6.2] S. D. Brotherton, Semicond, “Polycrystalline silicon thin film transistors,” Semicond. Science Tech, vol. 10, pp. 721-738, 1995
[6.3] K. Tanaka, H. Arai, S. Kohda, “Characteristics of offset-structure polycrystalline-silicon thin-film transistors,” IEEE Electron Device Letters., vol. 9, pp. 23-25, 1988
[6.4] Anish Kumar K. P., Johnny K. O. Sin, Cuong T. Nguyan, Ping K. KO, “Kink-free polycrystalline silicon double-gate elevated-channel thin-film transistors,” IEEE Transactions on Electron Devices., vol. 45, pp. 2514-2520, 1998
[6.5] G. Q. Lo, W. Ting, J. H. Ahn, D. L. Kwong, John Kuehne, “Thin fluorinated gate dielectrics grown by rapid thermal processingin O2 with diluted NF3,” IEEE Transactions on Electron Devices., vol. 39, pp. 148-153, 1992
[6.6] K. Y. Chou, M. J. Chen, ”Active circuits under wire bonding I/O pads in 0.13um eight-level Cu metal, FSG low-k inter-metal dielectric CMOS technology,” IEEE Electron Device Letters, vol. 22, pp. 466-468, 2001
[6.7] Chi-Chun Chen, Horng-Chih Lin, Chun-Yen Chang, Tiao-Yuan Huang, Chao-Hsin Chien, and Mong-Song Liang, “Improved Ultrathin Gate Oxide Integrity in p+-Polysilicon-Gate p-Channel Metal Oxide Semiconductor with Medium-Dose Fluorine Implantation,” Electrochemical and Solid-State Letters, vol. 3, no. 6, pp. 290-292, 2000
[6.8] Y. Nishioka, Y. Ohji, K. Mukai, T. Sugano, Y. Wang, T. P. Ma, “Dielectric characteristics of fluorinated ultra dry SiO2,” Applied Physics Letters., vol. 54, no. 12, pp. 1127–1129, 1989
[6.9] Y. Nishioka, K. Ohyu, Y. Ohji, N. Natuaki, K. Mukai, T. P. Ma,. “Hot-electron hardened Si-gate MOSFET utilizing F implantation,” IEEE Electron Device Letters., vol. 10, pp. 141–143, 1989
[6.10] Y. Nishioka, K. Ohyu, Y. Ohji, T. P. Ma, “Channel length and width. dependence of hot-carrier hardness in fluorinated MOSFET’s,” IEEE Electron Device Letters., vol. 10, pp. 540–542, 1989
[6.11] P. J.Wright, K. C.Saraswat, “The effect of fluorine in silicon dioxide gate dielectrics,” IEEE Transaction on Electron Devices., vol. 36, pp. 879-889, 1989
[6.12] Wright, N. Kasai, S. Inoue, K. Saraswat, “Hot-electron immunity of SiO2 dielectrics with fluorine incorporation,” IEEE Electron Device Letters., vol. 10, pp. 347-348, 1989
[6.13] I. W. Wu, T. Y. Huang, Warren B. Jackson, Alan G. Lewis, Anne Chiang, “Passivation kinetics of two types of defects in polysilicon TFT by plasma hydrogenation,” IEEE Electron Device Letters., vol. 12, pp. 181-183, 1991

Chapter 7
[7.1] D. Kahng, S. M. Sze, "A Floating Gate and Its Application to Memory Devices," Bell Syst. Tech. Journal., vol. 46, pp. 1288-1295, 1967
[7.2] J. D. Blauwe, “Nanocrystal Nonvolatile Memory Devices,” IEEE Transactions on Nanotechnology., vol. 1, pp. 72-77, 2002
[7.3] S. Tiwari, F. Rana, K. Chan, H. Hanafi, C. Wei, D. Buchanan, “Volatile and non-volatile memories in silicon with nano-crystal storage”, IEEE Int. Electron Devices Meeting Tech. Dig., pp. 521-524, 1995
[7.4] Y. C. King, T. J. King, C. Hu, “MOS memory using germanium nanocrystals formed by thermal oxidation of Si1-xGex”, IEEE Int. Electron Devices Meeting Tech. Dig., pp. 115-118, 1998
[7.5] J. J. Welser, S. Tiwari, S. Rishton, K. Y. Lee, Y. Lee, “Room temperature operation of a quantum-dot flash memory,” IEEE Electron Device Letters., vol. 18, pp. 278-280, 1997
[7.6] S. Tiwari, F. Rana, K. Chan, L. Shi, H. Hanafi, “Single charge and confinement effects in nano-crystal memories,” Applied Physics Letters., vol. 69, pp. 1232-1234, 1996
[7.7] M. Ostraat, J. De Blauwe, M. Green, D. Bell, H. Atwater, R. Flagan, “Ultraclean two-stage aerosol reactor for. production of oxide-passivated silicon nanoparticles for novel. memory devices,” Journal of Electrochemical Society., vol. 148, pp. 265–270, 2001
[7.8] Y. C. King, T. J. King, C. Hu, “A long refresh dynamic/quasi-nonvolatile memory device with 2-nm tunneling oxide,” IEEE Electon Device Letters., vol. 20, pp. 409-411, 1999
[7.9] L. Dori, A. Acovic, D. J. DiMaria, C. H. Hsu, “Optimized silicon rich oxide (SRO) deposition process for 5 V-only flash EEPROM applications,” IEEE Electron Device Letters., vol. 14, pp. 283-285, 1993
[7.10] M. Rosmeulen, E. Sleeckx, K. D. Meyer, IEEE Int. Electron Devices Meeting Tech. Dig., 189, 2002
[7.11] T. C. Chang, S. T. Yan, F. M. Yang, P. T. Liu, S. M. Sze, “Memory effect of oxide/SiC:O/oxide sandwiched structures,” Applied Physics Letters., vol. 84, pp. 2094-2096, 2004
[7.12] T. C. Chang, S. T. Yan, C. H. Hsu, M. T. Tang, J. F. Lee, Y. H. Tai, P. T. Liu, S. M. Sze, “A distributed charge storage with GeO2 nanodots,” Applied Physics Letters., vol. 84, pp. 2581-2583, 2004
[7.13] V. Ioannou-Sougleridis and A. G. Nassiopoulou, “Investigation of charging phenomena in silicon nanocrystal metal–oxide–semiconductor capacitors using ramp current–voltage measurements,” Journal of Applied Physics., vol. 94, pp. 4084-4087, 2003.
[7.14] T. C. Chang, S. T. Yan, P. T. Liu, C. W. Chen, S. H. Lin, S. M. Sze, “A novel approach of fabricating germanium nanocrystals for nonvolatile memory application,” Electrochemical and Solid-State Letters., vol. 7, pp. G17-19, 2004
[7.15] B. H. Koh, E. W. H. Kan, W. K. Chim, W. K. Choi, D. A. Antoniadis and E. A. Fitzgerald “Traps in germanium nanocrystal memory and effect on charge retention: Modeling and experimental measurements,” Journal of Applied Physics., vol. 97, pp. 124305, 2005.
[7.16] W. J. Tsai, C. C. Yeh, N. K. Zous, C. C. Liu, S. K. Cho, T. W, Samuel C. Pan, C. Y. Lu, “Positive Oxide Charge-Enhanced Read Disturb in a Localized Trapping Storage Flash Memory Cell,” IEEE Transactions on Electron Devices., vol. 51, pp. 434- 439, 2004

Chapter 8
[8.1] D. Kahng, S. M. Sze, "A Floating Gate and Its Application to Memory Devices," Bell Syst. Tech. Journal., vol. 46, pp. 1288-1295, 1967
[8.2] J. D. Blauwe, “Nanocrystal Nonvolatile Memory Devices,” IEEE Transactions on Nanotechnology., vol. 1, pp. 72-77, 2002
[8.3] S. Tiwari, F. Rana, K. Chan, H. Hanafi, C. Wei, D. Buchanan, “Volatile and non-volatile memories in silicon with nano-crystal storage”, IEEE Int. Electron Devices Meeting Tech. Dig., pp. 521-524, 1995
[8.4] Y. C. King, T. J. King, C. Hu, “MOS memory using germanium nanocrystals formed by thermal oxidation of Si1-xGex”, IEEE Int. Electron Devices Meeting Tech. Dig., pp. 115-118, 1998
[8.5] J. J. Welser, S. Tiwari, S. Rishton, K. Y. Lee, Y. Lee, “Room temperature operation of a quantum-dot flash memory,” IEEE Electron Device Letters., vol. 18, pp. 278-280, 1997
[8.6] S. Tiwari, F. Rana, K. Chan, L. Shi, H. Hanafi, “Single charge and confinement effects in nano-crystal memories,” Applied Physics Letters., vol. 69, pp. 1232-1234, 1996
[8.7] M. Ostraat, J. De Blauwe, M. Green, D. Bell, H. Atwater, R. Flagan, “Ultraclean two-stage aerosol reactor for. production of oxide-passivated silicon nanoparticles for novel. memory devices,” Journal of Electrochemical Society., vol. 148, pp. 265–270, 2001
[8.8] Y. C. King, T. J. King, C. Hu, “A long refresh dynamic/quasi-nonvolatile memory device with 2-nm tunneling oxide,” IEEE Electon Device Letters., vol. 20, pp. 409-411, 1999
[8.9] L. Dori, A. Acovic, D. J. DiMaria, C. H. Hsu, “Optimized silicon rich oxide (SRO) deposition process for 5 V-only flash EEPROM applications,” IEEE Electron Device Letters., vol. 14, pp. 283-285, 1993
[8.10] M. Rosmeulen, E. Sleeckx, K. D. Meyer, IEEE Int. Electron Devices Meeting Tech. Dig., 189, 2002
[8.11] T. C. Chang, S. T. Yan, F. M. Yang, P. T. Liu, S. M. Sze, “Memory effect of oxide/SiC:O/oxide sandwiched structures,” Applied Physics Letters., vol. 84, pp. 2094-2096, 2004
[8.12] T. C. Chang, S. T. Yan, C. H. Hsu, M. T. Tang, J. F. Lee, Y. H. Tai, P. T. Liu, S. M. Sze, “A distributed charge storage with GeO2 nanodots,” Applied Physics Letters., vol. 84, pp. 2581-2583, 2004
[8.13] T. C. Chang, S. T. Yan, P. T. Liu, C. W. Chen, S. H. Lin, S. M. Sze, “A novel approach of fabricating germanium nanocrystals for nonvolatile memory application,” Electrochemical and Solid-State Letters., vol. 7, pp. G17-19, 2004
[8.14] M. Kanoun, A. Souifi, T. Baron, F. Mazen, “Electrical study of Ge-nanocrystal-based metal-oxide-semiconductor structures for p-type nonvolatile memory applications,” Applied Physics Letters., vol. 84, pp. 5079-5081, 2004
[8.15] Y. C. King, T. J. King, C. Hu, “Charge-trap memory device fabricated by oxidation of Si1-xGex,” IEEE Transaction on Electron Devices., vol. 48, pp. 696-700, 2001
[8.16] C. H. Tu, T. C. Chang, P. T. Liu, H.C Liu, C. C. Tsai, L. T. Chang, T. Y. Tseng, S. M. Sze, C. Y. Chang, “Formation of germanium nanocrystals embedded in silicon-oxygen-nitride layer,” Applied Physics Letters., vol. 89, pp. 052112, 2006

Chapter 9
[9.1] Y. C. King, T. J. King, C. Hu, “Charge-trap memory device fabricated by oxidation of Si1-xGex,” IEEE Transaction on Electron Devices., vol. 48, pp. 696-700, 2001
[9.2] M. Kanoun, A. Souifi, T. Baron, F. Mazen, “Electrical study of Ge-nanocrystal-based metal-oxide-semiconductor structures for p-type nonvolatile memory applications,” Applied Physics Letters., vol. 84, pp. 079-5081, 2004
[9.3] E. W. H. Kan, W. K. Choi, C. C. Leoy, W. K. Chim, D. A. Antoniadis, E. A. Fitzgerald, “Effect of annealing profile on defect annihilation, crystallinity and size distribution of germanium nanodots in silicon oxide matrix,” Applied Physics Letters., vol. 83, pp. 2058-2060, 2003
[9.4] E. W. H. Kan, W. K. Choi, W. K. Chim, E. A. Fitzgerald, D. A. Antoniadis “Origin of charge trapping in germanium nanocrystal embedded SiO2 system: Role of interfacial traps?,” Journal of Applied Physics., vol. 95, pp. 3148-3152, 2004
[9.5] F. K. LeGoues, R. Rosenberg, T. Nguyen, F. Himpsel, B. S. Meyerson, “Oxidation studies of SiGe,” Journal of Applied Physics., vol. 65, pp. 1724-1728, 1989
[9.6] J. Eugene, F. K. LeGoues, V. P. Kesan, S. S. Iyer, F. M. d’Heurle, “Diffusion versus oxidation rates in silicon-germanium alloys,” Applied Physics Letters., vol. 59, pp. 78-80, 1991
[9.7] J. Rappich, I. Sieber, R. Knippelmeyer, “Enhanced Passivation of the Oxide/SiGe Interface of SiGe Epitaxial Layers on Si by Anodic Oxidation,” Electrochemical Solid-State Letters., vol. 4, pp. B11-B13, 2001
[9.8] C. H. Tu, T. C. Chang, P. T. Liu, H. C Liu, C. C. Tsai, L. T. Chang, T. Y. Tseng, S. M. Sze, C. Y. Chang, “Formation of germanium nanocrystals embedded in silicon-oxygen-nitride layer,” Applied Physics Letters., vol. 88, pp. 112105, 2006
[9.9] F. K. LeGoues, R. Rosenberg, T. Nguyen, F. Himpsel, B.S. Meyerson, “Oxidation studies of SiGe,” Journal of Applied Physics., vol. 65, pp. 1724-1728, 1989
[9.10] J. Eugene, F. K. LeGoues, V. P. Kesan, S. S. Iyer, F. M. d’Heurle, “Diffusion versus oxidation rates in silicon-germanium alloys,” Applied Physics Letters., vol. 59, pp. 78-80, 1991
[9.11] J. Rappich, I. Sieber, R. Knippelmeyer, “Enhanced passivation of the oxide/SiGe interface of SiGe epitaxial layers on Si by anodic oxidation,” Electrochemical Solid-State Letters, vol. 4, pp. B11-B13, 2001
[9.12] T. C. Chang, S. T. Yan, P. T. Liu, C. W. Chen, S. H. Lin, S. M. Sze, “A novel approach of fabricating germanium nanocrystals for nonvolatile memory application,” Electrochemical and Solid-State Letters., vol. 7, pp. G17-19, 2004
[9.13] T. C. Chang, S. T. Yan, C. H. Hsu, M. T. Tang, J. F. Lee, Y. H. Tai, P. T. Liu, S. M. Sze, “A distributed charge storage with GeO2 nanodots,” Applied Physics Letters., vol. 84, pp. 2581-2583, 2004

Chapter 10
[10.1] D. Kahng, S. M. Sze, “A Floating Gate and Its Application to Memory Devices,” Bell Syst. Tech. Journal., vol. 46, pp. 1288-1295, 1967
[10.2] J. D. Blauwe, “Nanocrystal Nonvolatile Memory Devices,” IEEE Transactions on Nanotechnology., vol. 1, pp. 72-77, 2002
[10.3] S. Tiwari, F. Rana, K. Chan, H. Hanafi, C. Wei, D. Buchanan, “Volatile and non-volatile memories in silicon with nano-crystal storage”, IEEE Int. Electron Devices Meeting Tech. Dig., pp. 521-524, 1995
[10.4] J. J. Welser, S. Tiwari, S. Rishton, K. Y. Lee, Y. Lee, “Room temperature operation of a quantum-dot flash memory,” IEEE Electron Device Letters., vol. 18, pp. 278-280, 1997
[10.5]Y. C. King, T. J. King, C. Hu, “MOS memory using germanium nanocrystals formed by thermal oxidation of Si1-xGex,” IEEE Int. Electron Devices Meeting Tech. Dig., pp. 115-118, 1998
[10.6] Y. C. King, T. J. King, C. Hu, “Charge-trap memory device fabricated by oxidation of Si1-xGex,” IEEE Transaction on Electron Devices., vol. 48, pp. 696-700, 2001
[10.7] M. Kanoun, A. Souifi, T. Baron, F. Mazen, “Electrical study of Ge-nanocrystal-based metal-oxide-semiconductor structures for p-type nonvolatile memory applications,” Applied Physics Letters., vol. 84, pp. 5079-5081, 2004
[10.8] E. W. H. Kan, W. K. Choi, C. C. Leoy, W. K. Chim, D. A. Antoniadis, E. A. Fitzgerald, “Effect of annealing profile on defect annihilation, crystallinity and size distribution of germanium nanodots in silicon oxide matrix”, Applied Physics Letters., vol. 83, pp. 2058-2060, 2003
[10.9] E. W. H. Kan, W. K. Choi, W. K. Chim, E. A. Fitzgerald, D. A. Antoniadis “Origin of charge trapping in germanium nanocrystal embedded SiO2 system: Role of interfacial traps?,” Journal of Applied Physics., vol. 95, pp. 3148-3152, 2004
[10.10] F. K. LeGoues, R. Rosenberg, T. Nguyen, F. Himpsel, B. S. Meyerson, “Oxidation studies of SiGe,” Journal of Applied Physics., vol. 65, pp. 1724-1728, 1989
[10.11] C. H. Tu, T. C. Chang, P. T. Liu, H. C Liu, C. C. Tsai, L. T. Chang, T. Y. Tseng, S. M. Sze, C. Y. Chang, “Formation of germanium nanocrystals embedded in silicon-oxygen-nitride layer,” Applied Physics Letters., vol. 88, pp. 112105, 2006
[10.12] F. K. LeGoues, R. Rosenberg, T. Nguyen, F. Himpsel, B.S. Meyerson, “Oxidation studies of SiGe,” Journal of Applied Physics., vol. 65, pp. 1724-1728, 1989
[10.13] J. Eugene, F. K. LeGoues, V. P. Kesan, S. S. Iyer, F. M. d’Heurle, “Diffusion versus oxidation rates in silicon-germanium alloys,” Applied Physics Letters., vol. 59, pp. 78-80, 1991
[10.14] J. Rappich, I. Sieber, R. Knippelmeyer, “Enhanced passivation of the oxide/SiGe interface of SiGe epitaxial layers on Si by anodic oxidation,” Electrochemical Solid-State Letters., vol. 4, pp. B11-B13, 2001
[10.15] T. C. Chang, S. T. Yan, C. H. Hsu, M. T. Tang, J. F. Lee, Y. H. Tai, P. T. Liu, S. M. Sze, “A distributed charge storage with GeO2 nanodots,” Applied Physics Letters., vol. 84, pp. 2581-2583,2004
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