跳到主要內容

臺灣博碩士論文加值系統

(44.220.247.152) 您好!臺灣時間:2024/09/10 22:26
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

: 
twitterline
研究生:許義明
研究生(外文):Yi-Ming Sheu
論文名稱:先進金氧半場效電晶體對於佈局之依賴效應
論文名稱(外文):Layout Dependent Effect on Advanced MOSFETs
指導教授:陳明哲陳明哲引用關係
指導教授(外文):Ming-Jer Chen
學位類別:博士
校院名稱:國立交通大學
系所名稱:電子工程系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:英文
論文頁數:136
中文關鍵詞:摻雜擴散機械應力應變淺溝隔絕金氧半場效電晶體遷移率井邊緣親近離子散射SPICE模擬
外文關鍵詞:dopant diffusionmechanical stressstrainshallow trench isolationMOSFETmobilityWell-Edge Proximityion scatteringSPICEmodeling and simulation
相關次數:
  • 被引用被引用:0
  • 點閱點閱:494
  • 評分評分:
  • 下載下載:53
  • 收藏至我的研究室書目清單書目收藏:0
次100奈米先進互補金氧半技術中之金氧半場效電晶體對於佈局的依賴效應已經日趨明顯。本篇論文展示了兩個主要引起金氧半場效電晶體行為對於佈局依賴性的要素 ­ 製程引起的機械應力效應和井邊緣親近效應。
在製程引起的機械應力效應方面,第一點,本論文使用閘極長度為65奈米的先進互補金氧半技術完成了實驗之設計與執行。第二點,以包含種種機械應力來源並考慮全製程的數值運算完整的模擬了整個金氧半場效電晶體結構。第三點,提出了一個新的應力相依的摻雜擴散模型並將之加入於數值模擬軟體中,而模擬結果符合了矽晶片實驗實驗範圍內之金氧半場效電晶體的次臨限(subthreshold)特性。第四點,本論文探討了淺溝渠及熱氧化製程引起的機械應力和金氧半場效電晶體開狀態(on-state)對於佈局的依賴效應的關係,發展出一組精簡、可變化規模(scalable)的新積體電路模擬程式(SPICE)模型來解釋淺溝渠機械應力對金氧半場效電晶體性能的影響,並且成功預測晶片實驗中各條件的實驗結果。
本論文亦使用了次100奈米先進互補金氧半技術詳細探討了由離子佈植時邊界摻雜散射引起的井邊緣親近效應。晶片實驗和技術電腦輔助設計(TCAD)模擬被用來從物理和製程的角度探討這個效應。蒙地卡羅離子散射模型和技術電腦輔助設計模擬提供了金氧半場效電晶體內部如何形成改變的物理了解。一個基於此物理了解的精簡新積體電路模擬程式模型被提出來並且以晶片實驗中各測試組結果完成此模型之校正。
The layout dependent effect on the MOSFETs characteristics has become more and more significant in advanced sub-100nm CMOS technologies. This dissertation demonstrates the experimental results, theories and modeling of two main factors making MOSFET behaviors layout dependent – process induced mechanical stress effect and well-edge proximity effect.
For the process induced mechanical stress effect, first, complete experiments are designed and conducted using novel CMOS technology with a minimum physical gate length of 65nm to investigate the mechanical stress effect. Second, full-process numerical simulations are performed for modeling complete MOSFET structures containing various mechanical stress sources. Third, a new stress-dependent dopant diffusion model is proposed and is implemented into the simulation software and the simulation results match MOSFET subthreshold characteristics of the silicon wafer experiment within the design space. Fourth, the relationship between layout dependence of MOSFET on-state characteristics and mechanical stress caused by shallow trench isolation (STI) and thermal oxidation has been investigated, and a new compact and scaleable SPICE model accounting for the STI mechanical stress effect on MOSFET electrical performance is developed and successfully matches the experimental data under various conditions.
The well-edge proximity effect caused by the boundary dopant scattering during ion implantations is further explored using a sub-100nm CMOS technology in detail. TCAD simulations together with silicon wafer experiments have been conducted to investigate the impact of this effect from a physics and process perspective. The Monte Carlo ion scattering model and TCAD simulations provide a physical understanding of how the internal changes of the MOSFETs are formed. A new compact model for SPICE is proposed using physics-based understanding and has been calibrated using experimental silicon test sets.
Content (Index)
Abstract (in Chinese) i
Abstract (in English) iii
Acknowledgements v
Content (Index) viii
Table Captions x
Figure Captions xi
Chapter 1 Introduction 1
1.1 Overview 1
1.2 TCAD modeling 5
1.3 Dissertation Organization 8
References 9
Chapter 2 Dopant Diffusion Under Mechanical Stress 21
2.1 Preface 21
2.2 Stress-dependent Diffusion Model and Modeling Methodology 23
2.2.1 Model Description 23
2.2.2 Modeling Methodology 25
2.2.3 Experiment on MOSFET Threshold Voltages and Modeling Results 27
2.3 Experiment on MOSFET Subthreshold Leakage with Stress-Dependent Transient–Enhanced-Diffusion Effect Included 32
2.4 Anisotropic Diffusion Derivation for Uniaxial Strain Cases 36
References 44
Chapter 3 Mechanical Stress Effects on MOSFET Performances and SPICE Modeling 66
3.1 Preface 66
3.2 STI Mechanical Stress Effects on Modern MOSFET Drive Currents 66
3.2.1 Layout Matrix and Experimental Results 66
3.2.2 Simulation and Systematic Analysis 68
3.3 SPICE Model for STI Mechanical Stress Effect 70
3.3.1 MOSFET Measurement Data Analysis 70
3.3.2 Model Development 71
3.3.3 Model Verification 74
3.3.4 Impact on Circuit Design 76
References 78
Chapter 4 Well-Edge Proximity Effect 102
4.1 Preface 102
4.2 Ion Scattering Physics and Modeling 102
4.3 TCAD Numerical Simulation 105
4.4 Compact Model for SPICE 107
References 111
Chapter 5 Summary and Future Work 123
5.1 Summary 123
5.2 Recommendations for Future Work 125
Vita 127
Publication list 128
References
[1.1] International technology roadmap for semiconductors, 2005 edition, executive summary.
[1.2] G. Scott, J. Lutze, M. Rubin, F. Nouri, and M. Manley, “NMOS drive current reduction caused by transistor layout and trench isolation induced stress,” in IEDM Tech. Dig., Dec. 1999, pp. 827-830.
[1.3] R. A. Bianchi, G. Bouche, and O. Roux-dit-Buisson, “Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance,” in IEDM Tech. Dig., Dec. 2002, pp. 117-120.
[1.4] Y. M. Sheu, Kelvin Y. Y. Doong, C. H. Lee, M. J. Chen, and C. H. Diaz, “Study on STI mechanical stress induced variations on advanced CMOSFETs,” in Proc. of ICMTS, Mar. 2003, pp. 205-208.
[1.5] K. W. Su, Y. M. Sheu, C. K. Lin, S. J. Yang, W. J. Liang, X. Xi, C. S. Chiang, J. K. Her, Y. T. Chia, C. H. Diaz, and C. Hu, “A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics,” in Proc. of Custom Integrated Circuits Conference, Sep. 2003, pp. 245-248.
[1.6] S. Ito, H. Namba, K. Yamaguchi, T. Hirata, K. Ando, S. Koyama, S. Kuroki, N. Ikezawa, T. Suzuki, T. Saitoh, and T. Horiuchi, “Mechanical stress effect of etch-stop nitride and its impact on deep submicron transistor design,” in IEDM Tech. Dig., Dec. 2000, pp. 247-250.
[1.7] C. H. Ge, C. C. Lin, C. H. Ko, C. C. Huang, Y. C. Huang, B. W. Chen, B. C. Perng, C. C. Sheu, P. Y. Tsai, L. G. Yao, C. L. Wu, T. L. Lee, C. J. Chen, C. T. Wang, S. C. Lin, Y. C. Yeo, and C. Hu, “Process-strained Si (PSS) CMOS technology featuring 3D strain engineering,” in IEDM Tech. Dig., Dec. 2003, pp. 73-76.
[1.8] K. Rim, J, Chi, H. Chen, K.A. Jenkins, T. Kanarsky, K. Lee, A. Mocuta, H. Zhu, R. Roy, J. Newbury, J. Ott, K. Petrarca, P.M. Mooney, D. Lacey, K. Koester, K. Chan, D. Boyd, M. Ieong, and H.-S. Wong, “Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs,“ In VSLI Symp. Tech. Dig., Jun. 2002, pp. 98–99.
[1.9] J. Jung, S. Yu, M. L. Lee, J. L. Hoyt, E. A. Fitzgerald, and D. A. Antoniadis “Mobility Enhancement in Dual-Channel P-MOSFETs,” IEEE Trans. Electron Devices, vol. 51, pp. 1424-1431, September 2004.
[1.10] S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C. H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Z. Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, P. Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy, “A 90-nm logic technology featuring strained-silicon,” IEEE Trans. Electron Devices, vol. 51, pp. 1790-1797, November 2004.
[1.11] K. W. Ang, K. J. Chui, V. Bliznetsov, A. Du, N. Balasubramanian, M. F. Li, G. Samudra, and Y. C. Yeo, ” Enhanced performance in 50 nm N-MOSFETs with silicon-carbon source/drain regions,” in IEDM Tech. Dig., Dec. 2004, pp. 1069-1071.
[1.12] S. Tyagi, C. Auth, P. Bai, G. Curello, H. Deshpande, S. Gannavaram, O. Golonzka, R. Heussner, R. James, C. Kenyon, S-H Lee, N. Lindert, M. Liu, R. Nagisetty, S. Natarajan, C. Parker, J. Sebastian, B. Sell, S. Sivakumar, A. St Amour, K. Tone “An advanced low power, high performance, strained channel 65nm technology,” in IEDM Tech. Dig., Dec. 2005, pp. 245-248.
[1.13] J. Damiano, C. K. Subramanian, M. Gibson, Y.-S. Feng, L. Zeng, J. Sebek, E. Deeters, C. Feng, T. McNelly, M. Blackwell, H. Nguyen, H.Tian, J. Scott, J. Zaman, C. Honcik, M. Miscione, K. Cox, and J. D. Hayden, “Characterization and elimination of trench dislocations,” in VSLI Symp. Tech. Dig., Jun. 1998, pp. 212–213.
[1.14] T. K. Kim, D. H. Kim, J. K. Park, T. S. Park, Y. K. Park, H. J. Lee, K. Y. Lee, J. T. Kong, J. W. Park, “Modeling of cumulative thermo-mechanical stress (CTMS) produced by the Shallow trench isolation process for. 1Gb. DRAM and beyond” in IEDM Tech. Dig., Dec. 1998, pp. 145-148.
[1.15] D. Ha, C. Cho, D. Shin, G. H. Koh, T. Y. Chung, and K. Kim, “Anomalous junction leakage current induced by STI dislocations and its impact on dynamic random access memory devices,” IEEE Trans. Electron Devices, vol. 46, pp. 940-946, May 1999.
[1.16] J. W. Sleight, C. Lin, and G. J. Grula, “Stress Induced Defects and Transistor Leakage for Shallow Trench Isolated SOI,” IEEE Electron Devices Lett., vol. 20, pp. 248-250, Dec. 1999.
[1.17] Z. K. Lee, M. B. McIlrath, and D. A. Antoniadis, “Two-dimensional doping profile characterization of MOSFET’s by inverse modeling using I-V characteristics in the subthreshold region,” IEEE Trans. Electron Devices, vol. 46, pp. 1640-1649, August 1999.
[1.18] G. Dorda, “Peizoresistance in quantized conduction bands in silicon inversion layers,” J. Appl. Phys., vol. 42, pp. 2053-2060, April 1971.
[1.19] J. Welser, J. L. Hoyt, and J. F. Gibbons, “Electron mobility enhancement in strained-Si N-type metal-oxide-semiconductor field-effect transistors,” IEEE Electron Device Lett., vol. 15, pp. 100–102, Feb. 1994.
[1.20] A. Lochtefeld and D. A. Antoniadis, “Investigating the relationship between electron mobility and velocity in deeply scaled NMOS via mechanical stress,” IEEE Electron Device Lett., vol. 22, pp. 591–593, Aug. 2001.
[1.21] S. Takagi, J. L. Hoyt, J. J. Welser, and J. F. Gibbons, “Comparative study of phonon-limited mobility of two-dimensional electrons in strained and unstrained Si metal–oxide–semiconductor field-effect transistors,’ J. Appl. Phys., pp. 1567-1577, vol. 80, August 1996.
[1.22] E. X. Wang, P. Matagne, L. Shifren, B. Obradovic, R. Kotlyar, S. Cea, M. Stettler, and M. D. Giles, “Physics of hole transport in strained silicon MOSFET inversion layers,” IEEE Trans. Electron Devices, vol. 53, pp. 1840-1851, August 2006.
[1.23] X. F. Fan, X. Wang, B. Winstead, L. F. Register, U. Ravaioli, and S. K. Banerjee, “MC Simulation of Strained-Si MOSFET With Full-Band Structure and Quantum Correction,” IEEE Trans. Electron Devices, vol. 51, pp. 962-970, June 2004.
[1.24] S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C. H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Z. Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, P. Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy, “A 90-nm logic technology featuring strained-silicon,” IEEE Trans. Electron Devices, vol. 51, pp. 1790-1797, November 2004.
[1.25] S. Thompson, G. Sun, K. Wu, J. Lim, and T. Nishida, “Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs” in IEDM Tech. Dig., Dec. 2004, pp. 221-224.
[1.26] T. B. Hook, J. Brown, P. Cottrell, E. Adler, D. Hoyniak, J. Johnson, and R. Mann, “Lateral Ion Implant Straggle and Mask Proximity Effect,” IEEE Trans. Electron Devices, vol. 50, pp. 1946-1951, September 2003.
[1.27] K. W. Su, Y. M. Sheu, C. K. Lin, S. J. Yang, W. J. Liang, X. Xi, C. S. Chiang, J. K. Her, Y. T. Chia, C. H. Diaz, and C. Hu, “A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics,” in Proc. of Custom Integrated Circuits Conference, Sep. 2003, pp. 245-248.
[1.28] J. Watts, K. W. Su, and M.Basel, “Netlisting and Modeling Well-Proximity Effects,” IEEE Trans. Electron Devices, vol. 53, pp. 2179-2186, September 2006.
[1.29] Y. M. Sheu, K. W. Su, S. Tian, S. J. Yang, C. C. Wang, M. J. Chen, and S. Liu, “Modeling the Well-Edge Proximity Effect in Highly Scaled MOSFETs,” IEEE Trans. Electron Devices, vol. 53, pp. 2792-2798, November 2006.
Berkeley Short-channel IGFET Model (BSIM) version 4.5.0 manual, chapter 14.
[2.1] Y. M. Sheu, Kelvin Y. Y. Doong, C. H. Lee, M. J. Chen, and C. H. Diaz, “Study on STI mechanical stress induced variations on advanced CMOSFETs,” in Proc. of ICMTS, Mar. 2003, pp. 205-208.
[2.2] R. A. Bianchi, G. Bouche, and O. Roux-dit-Buisson, “Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance,” in IEDM Tech. Dig., Dec. 2002, pp. 117-120.
[2.3] K. W. Su, Y. M. Sheu, C. K. Lin, S. J. Yang, W. J. Liang, X. Xi, C. S. Chiang, J. K. Her, Y. T. Chia, C. H. Diaz, and C. Hu, “A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics,” in Proc. of Custom Integrated Circuits Conference, Sep. 2003, pp. 245-248.
[2.4] A. Toda, N. Ikarashi, H. Ono, S. Ito, T. Toda, and K. Imai, “Local lattice strain distribution around a transistor channel in metal-oxide-semiconductor devices,” Appl. Phys. Lett., vol. 79, pp. 4243-4245, Dec. 2001.
[2.5] D. Chidambarrao, J. P. Peng, and G. R. Srinivasan, “Stresses in silicon substrates near isolation trenches,” J. Appl. Phys., pp. 4816-4822, vol. 70, Nov. 1991.
[2.6] Y. M. Sheu, C. S. Chang, H. C. Lin, S. S. Lin, C. H. Lee, C. C. Wu, M. J. Chen, and C. H. Diaz, “Impact of STI mechanical stress in highly scaled MOSFETs,” in Int. Symp. VLSI-TSA, Oct. 2003, pp. 76-79.
[2.7] V. Senez, T. Hoffmann, E. Robiliart, G. Bouche, H. Jaouen, M. Lunenborg, and G. Carnevale, “Investigations of stress sensitivity of 0.12 CMOS technology using process modeling,” in IEDM Tech. Dig., Dec. 2001, pp. 831-834.
[2.8] V. Senez, A. Armigliato, I. De Wolf, G. Carnevale, R. Balboni, S. Frabboni, and A. Benedetti, “Strain determination in silicon microstructures by combined convergent beam electron diffraction, process simulation, and micro-Rama spectroscopy,” J. Appl. Phys., vol. 94, pp. 5574-5583, Nov. 2003.
[2.9] B. Dietrich, V. Bukalo, A. Fischer, K. F. Dombrowski, E. Bugiel, B. Kuck, and H. H. Richter, “Raman-spectroscopic determination of inhomogeneous stress in submicron silicon devices,” Appl. Phys. Lett., vol. 82, pp. 1176-1178, Feb. 2003.
[2.10] K. Rim, J. L. Hoyt, and J. F. Gibbons, “Fabrication and analysis of deep submicron strained-Si N-MOSFET’s,” IEEE Trans. Electron Devices, vol. 47, pp. 1406-1415, July 2000.
[2.11] S. Ito, H. Namba, K. Yamaguchi, T. Hirata, K. Ando, S. Koyama, S. Kuroki, N. Ikezawa, T. Suzuki, T. Saitoh, and T. Horiuchi, “Mechanical stress effect of etch-stop nitride and its impact on deep submicron transistor design,” in IEDM Tech. Dig., Dec. 2000, pp. 247-250.
[2.12] A. Lochtefeld and D. A. Antoniadis, “Investigating the relationship between electron mobility and velocity in deeply scaled NMOS via mechanical stress,” IEEE Electron Devices Lett., vol. 22, pp. 591-593, Dec. 2001.
[2.13] A. Hamada, T. Furusawa, N. Saito, and E. Takeda, “A new aspect of mechanical stress effects in scaled MOS devices,” IEEE Trans. Electron Devices, vol. 38, pp. 895-900, Apr. 1991.
[2.14] G. Scott, J. Lutze, M. Rubin, F. Nouri, and M. Manley, “NMOS drive current reduction caused by transistor layout and trench isolation induced stress,” in IEDM Tech. Dig., Dec. 1999, pp. 827-830.
[2.15] N. E. B. Cowern, P. C. Zlam, van der Sluis, D. J. Gravesteijn, and W. B. Boer, “Diffusion in strained Si(Ge),” Phy. Rev. Lett., vol. 72, pp. 2585-2588, Apr. 1994.
[2.16] S. Chaudhry and M. E. Law, “The stress assisted evolution of point and extended defects in silicon,” J. Appl. Phys., vol. 82, pp. 1138-1146, Aug. 1997.
[2.17] S. T. Ahn, H. W. Kennel, J. D. Plummer, and W. A. Tiller, “Film stress-related vacancy supersaturation in silicon under low-pressure chemical vapor deposited silicon nitride films,” J. Appl. Phys., vol. 64, pp. 4914-4918, Nov. 1988.
[2.18] M. J. Aziz, “Thermodynamics of diffusion under pressure and stress: Relation to point defect mechanisms,” Appl. Phys. Lett, vol. 70, pp. 2810-2812, May 1997.
[2.19] N. R. Zangenberg, J. Fage-Pedersen, J. L. Hansen, and A. Nylandsted Larsen, “Boron and phosphorus diffusion in strained and relaxed Si and SiGe,” J. Appl. Phys., vol. 94, pp. 3883-3890, Sep. 2003.
[2.20] M. Diebel: Ph. D thesis of University of Washington, Seattle, WA.
[2.21] Synopsys TSUPREM-4 User Guide, version 2003.06, U.S.A.: Synopsys Inc., June 2003.
[2.22] H. Park, K. S. Jones, J. A. Slinkman, and M. E. Law, “The effects of strain on dopant diffusion in silicon,” in IEDM Tech. Dig., Dec. 1993, pp. 303-306.
[2.23] Z. K. Lee, M. B. McIlrath, and D. A. Antoniadis, “Two-dimensional doping profile characterization of MOSFET’s by inverse modeling using I-V characteristics in the subthreshold region,” IEEE Trans. Electron Devices, vol. 46, pp. 1640-1649, August 1999.
[2.24] Y. M. Sheu, S. J. Yang, C. C. Wang, C. S. Chang, L. P. Huang, T. Y. Huang, M. J. Chen, and C. H. Diaz, “Modeling mechanical stress effect on dopant diffusion in scaled MOSFETs,” IEEE Trans. Electron Devices, vol. 52, pp. 30-38, January 2005.
[2.25] M. J. Aziz, Y. Zhao, H. J. Gossmann, S. Mitha, S. P. Smith, and D. Schiferl, “Pressure and stress effects on the diffusion of B and Sb in Si and Si-Ge alloys,” Phys. Rev. B, vol. 64, pp. 054101-1-054101-20, June 2006.
[2.26] Y. Zhao, M. J. Aziz, H. J. Gossmann, S. Mitha, and D. Schiferl, ”Activation volume for boron diffusion in silicon and implications for strained films,” Appl. Phys. Lett., vol. 74, pp. 31-33, Jan. 1999.
[2.27] Y. Zhao, M. J. Aziz, H. J. Gossmann, S. Mitha, and D. Schiferl, ”Activation volume for antimony diffusion in silicon and implications for strained films,” Appl. Phys. Lett., vol. 75, pp. 941-943, Aug. 1999.
[2.28] H. F. Wolf, “Semiconductors,” John Wiley & Sons, Inc. 1971.
[2.29] S. T. Dunham, M. Diebel, C. Ahn, and C. L. Shih, “Calculations of effect of anisotropic stress/strain on dopant diffusion in silicon under equilibrium and nonequilibrium conditions,” J. Vac. Sci. Technol. B, vol. 24, pp. 456-461, January 2006.
[3.1] G. Scott, J. Lutze, M. Rubin, F. Nouri, and M. Manley, “NMOS drive current reduction caused by transistor layout and trench isolation induced stress,” in IEDM Tech. Dig., Dec. 1999, pp. 827-830.
[3.2] C. C. Wu, Y. K. Leung, C. S. Chang, M. H. Tsai, H. T. Huang, D. W. Lin, Y. M. Sheu, C. H. Hsieh, W. J. Liang, L. K. Han, W. M. Chen, S. Z. Chang, S. Y. Wu, S. S. Lin, H. C. Lin, C. H. Wang, P. W. Wang, T. L. Lee, C. Y. Fu, C. W. Chang, S. C. Chen, S. M. Jang, S. L. Shue, H. T. Lin, Y. C. See, Y. J. Mii, C. H. Diaz, Burn J. Lin, M. S. Liang, Y. C. Sun, “A 90-nm CMOS device technology with high-speed, general-purpose, and low-leakage transistors for system on chip applications,” in IEDM Tech. Dig., Dec. 2002, pp. 65-68.
[3.3] M. V. Fischetti and S. E. Laux, “Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys,” J. Appl. Phys., pp. 2234-2252, vol. 80, Nov. 1996.
[3.4] V. Senez, T. Hoffmann, E. Robiliart, G. Bouche, H. Jaouen, M. Lunenborg, and G. Carnevale, “Investigations of stress sensitivity of 0.12 CMOS technology using process modeling,” in IEDM Tech. Dig., Dec. 2001, pp. 831-834.
[3.5] T. Kuroi, T. Uchida, K. Horita, M. Sakai, Y. Inoue,and T. Nishimura, “Stress analysis of shallow trench isolation for 256 M DRAM and beyond,” in IEDM Tech. Dig., Dec. 1998, pp. 141-144.
[3.6] A. Lochtefeld and D. A. Antoniadis, “Investigating the relationship between electron mobility and velocity in deeply scaled NMOS via mechanical stress,” IEEE Electron Devices Lett., vol. 22, pp. 591-593, Dec. 2001.
[3.7] H. Park, K. S. Jones, J. A. Slinkman, and M. E. Law, “The effects of strain on dopant diffusion in silicon,” in IEDM Tech. Dig., Dec. 1993, pp. 303-306.
[3.8] R. A. Bianchi, G. Bouche, and O. Roux-dit-Buisson, “Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance,” in IEDM Tech. Dig., Dec. 2002, pp. 117-120.
[4.1] G. Scott, J. Lutze, M. Rubin, F. Nouri, and M. Manley, “NMOS drive current reduction caused by transistor layout and trench isolation induced stress,” in IEDM Tech. Dig., Dec. 1999, pp. 827-830.
[4.2] R. A. Bianchi, G. Bouche, and O. Roux-dit-Buisson, “Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance,” in IEDM Tech. Dig., Dec. 2002, pp. 117-120.
[4.3] K. W. Su, Y. M. Sheu, C. K. Lin, S. J. Yang, W. J. Liang, X. Xi, C. S. Chiang, J. K. Her, Y. T. Chia, C. H. Diaz, and C. Hu, “A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics,” in Proc. of Custom Integrated Circuits Conference, Sep. 2003, pp. 245-248.
[4.4] T. B. Hook, J. Brown, P. Cottrell, E. Adler, D. Hoyniak, J. Johnson, and R. Mann, “Lateral Ion Implant Straggle and Mask Proximity Effect,” IEEE Trans. Electron Devices, vol. 50, pp. 1946-1951, September 2003.
[4.5] S. Tian, “Predictive Monte Carlo ion implantation simulator from sub-keV to above 10 MeV”, J. Appl. Phys., vol. 93, pp. 5893-5904, May 2003.
[4.6] J. F. Ziegler, J. P. Biersack, and U. Littmark, “The Stopping and Range of Ion in Solids”, Pergamon, New York, 1985.
[4.7] J. Lindhard and M.Scharff, “Energy Dissipation by Ions in the keV region”, Phys. Rev., vol. 124, pp. 128-130, October 1961.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top