臺灣博碩士論文加值系統

本論文提出並實作一種具有自我對準能力之複晶矽奈米線薄膜電晶體，以及一種應用於解析熱載子衰退的新穎測試結構。首先，我們描述奈米線薄膜電晶體之製程，及如何製作此複晶矽奈米線的製程參數。我們也審視了影響奈米線尺寸及形狀之因子。這個製程非常簡單，不牽涉到複雜且昂貴的電子束微影或是深紫外光微影設備。

我們研究並討論了奈米線薄膜電晶體的開狀態特性，包括剛製成的元件及經過電漿處理的元件，然後討論了電漿處理及尺寸對於電特性的影響。與傳統平面結構的元件比較，此奈米線通道的優點包括有：絕佳的開電流密度及對短通道效應有較佳的控制能力等等。此外，由於奈米線的寬度很窄，在進行氫化的時候能夠更夠效率地使元件的特性改善。

我們也研究了奈米線薄膜電晶體其獨特的關狀態漏電流機制。產生於閘極與汲極間重疊區域的閘極引發汲極漏電流(gate-induced drain leakage, GIDL)，被發現是造成此一異常漏電流的元兇。我們仔細檢驗了此一異常漏電流的產生原因，以及電漿處理對於此漏電流的影響。我們發現此一電流起因於在閘極與汲極介面的低掺雜區域，此區域引發了一條額外的漏電流路徑。在檢驗了漏電流的起因之後，我們提出並實際驗證了數種減少此一漏電流的方案。這些方案包括了快速熱退火(Rapid thermal annealing, RTA)、在閘極與汲極間插入一層氮化矽、以及改使用複晶矽鍺材料作為奈米線通道等。這數種方案的特色被逐一比較並加以討論。

我們也提出並實作了一種新穎的測試結構，可以解析薄膜電晶體中熱載子衰退所發生的位置及時間演變。此一新穎測試結構的製作方式與傳統的薄膜電晶體一樣容易，與現在的超大規模積體電路製程完全相容，並且不需要額外的光罩。我們檢視了此一測試元件所帶來之靈敏度的提昇以及在決定施壓條件時的優點，也探討了金屬後電漿處理對於熱載子衰退效應的影響。特別的是，我們在研究過程中，利用此一結構發現了兩種會造成臨界電壓漂移的機制。

由於此測試結構的高靈敏度及解析能力，使得在研究可靠度相關議題時，能夠直接利用此一測試結構直接觀察元件的衰退現象，不必再利用高電壓施壓條件下的結果，去推測元件在正常操作或是低電壓施壓條件之下的衰退現象，並可以比較元件在高低電壓施壓下的不同現象和機制。

我們也利用此一測試結構，研究了當元件操作於交流模式時，所產生的熱載子衰退現象。關於操作頻率、上升及下降時間都有詳細的探討。利用此一測試結構的特性，輸入訊號中各個準位階段其所對應到的損傷位置可以被定位出來。實驗結果顯示，損傷主要是當閘極訊號切換時，瞬間所產生的熱載子所導致。伴隨著偵測熱載子衰退時的高靈敏度，此一元件也可以應用於一般交流操作時的可靠度研究之用。

在此論文的最後一個部份，我們進行了關於缺陷能態密度的分析。在說明原理及方式之後，我們可以利用前述的測試元件萃取出當元件受到熱載子損傷之後，其能態密度分佈的變化。由於傳統元件在受到熱載子損傷後，通道中各部位的能態密度分佈將會變得不均勻，且局部的缺陷密度增加量將會在萃取能態密度分佈時被整體所稀釋，造成實務上萃取的困難。利用此一測試元件，我們可以萃取出各部位其能態密度分佈的變化，並重組成元件衰退後的真實分佈狀態，並利用元件模擬技術重現元件的次臨界特性曲線。

In this thesis, we proposed and demonstrated a poly-Si thin-film transistor with self-aligned nanowire channels, as well as a novel test structure suitable for resolving hot-carrier degradation. Firstly, the fabrication of proposed NWTFT was described, followed by the detail in poly-Si nanowire formation and investigation of the factors affecting size and shape of the nanowire. The fabrication is simple and does not involve costly lithography tools.

On-state characteristics of NWTFT were then examined and discussed, including as-fabircated and plasma-treated samples. The effects of post-metal treatment and geometric parameters on NWTFT were then discussed. The advantages of NWTFT were demonstrated by comparing with traditional planar structures. Such nanowire structure has been shown to be excellent in terms of on-current per unit width and controllability over short-channel effects. Owing to the fine nano-scale of NW width, hydrogenation would be very efficient for further performance improvement.

The unique off-state leakage mechanism of NWTFT was also investigated. A gate-induced drain leakage (GIDL), which is generated in the overlapped region between the gate and the drain, was uncovered as the major culprit for the anomalous leakage. The origin of the anomalous leakage was then examined, as well as the effect of post-metal treatment. This current was found to originate from the lightly-doped region at gate/drain interface, which induced an additional current path. After that, several modifications were proposed and demonstrated in order to alleviate the unique leakage. Rapid thermal annealing (RTA), inserted nitride mask, and poly Si1-XGeX were investigated and compared.

A tester, which can spatially and temporally resolve hot-carrier degradations, was proposed and demonstrated. The fabrication of the novel test structure is simple and compatible with standard ULSI processings without extra masking. Advantages in sensitivity and stress-condition determination were discussed, accompanying with the effects of post-metal plasma treatment on hot-carrier degradations. Specifically, we found that at least two mechanisms are responsible for the negative threshold voltage shift detected by monitor transistors. The high sensitivity and resolving capability of the novel test structure can also help researchers observe directly degradation phenomena occurring when devices are stressed under moderate or minor conditions.

We also studied the phenomena of hot-carrier degradation during AC operations using the proposed test structure. Effects of frequency, rising and falling times, were investigated and discussed. The phenomena of the hot-carrier degradation can be spatially resolved using the proposed tester. By applying such a tester to AC hot-carrier stressing, the relationship between different stages of input signal and resultant damage location can be established. The tester also showed a high sensitivity in detecting even mild AC degradation. The experiment provides unambiguous evidence that the damage occurs during the transient stages, with the aid of the test structure.

At the last part of the thesis, the analyses related to effective density-of-states distributions were performed. After the description of experimential procedures, effective density-of-states distributions of localized damaged regions were extracted using the aforementioned tester. The information revealed by the analyses was then discussed. The extracted density-of-states distributions for both unstressed and stressed films were used to conduct simulations for subthreshold characteristics of TFTs and compared with the experimental data. The combination of the proposed novel test structure and density-of-states extraction technique provides a powerful tool for resolving the non-uniform density-of-states distribution of TFTs after HC stressing, which is impossible using traditional testers.

Abstract (Chinese) i
Abstract (English) v
Acknowledgement (Chinese) ix
Contents xi
Table Captions xv
Figure Captions xvii
1 Introduction 1
1.1 An overview of poly-Si thin-film transistors: trends in the development 1
1.1.1 Efforts in mobility enhancement 2
1.1.2 Efforts in off-state leakage reduction 2
1.2 An introduction of silicon nanowires 3
1.3 Reliability issues in poly-Si TFTs 4
1.4 Motivation of this study 5
1.5 Organization of the thesis 6
2 Nanowire TFTs with Self-Aligned Poly-Si Channels 9
2.1 Background 9
2.2 Fabrication of nanowire TFTs 11
2.2.1 Device Structure 11
2.2.2 Process of fabrication 12
2.2.3 Formation of poly-Si nanowires 13
2.3 On-state Characteristics of nanowire TFTs 17
2.3.1 Characteristics of as-fabricated nanowire TFTs 18
2.3.2 Effects of post-metal treatment 19
2.3.3 Effects of geometric parameters of the nanowire channel 22
2.3.4 Features of TFTs in nano-scale regime 26
2.4 Summary 31
3 Off-state Characteristics of Nanowire TFTs 33
3.1 Introduction to off-state leakage in TFTs 33
3.1.1 General background 33
3.1.2 Proposed mechanisms for off-state leakage current 35
3.1.3 Methods for analyzing off-state leakage current 36
3.1.4 Methods for off-state leakage current reduction 37
3.2 Leakage current mechanism in NWTFTs 39
3.2.1 Origins of off-state leakage current in NWTFTs 40
3.2.2 Effects of post-metal plasma treatment 44
3.3 Reduction of off-state leakage current in NWTFTs 46
3.3.1 Proposed methods for leakage current reduction in NWTFTs 47
3.3.2 Effects of rapid thermal annealing (RTA) 47
3.3.3 Effects of additional nitride hard mask in gate/drain overlap region 48
3.3.4 Effects of Si1-XGeX channel material 51
3.3.5 Comparisons and discussion among proposed methods 52
3.4 Summary 55
4 Investigation of Hot-carrier Degradation Using a Novel Test Structure 57
4.1 Introduction of hot-carrier effect (HCE) 57
4.1.1 Hot-carrier degradation in MOSFETs 59
4.1.2 Challenges in hot-carrier analysis of TFTs 60
4.2 Fabrication and operating principle of HCTFT 61
4.3 Spatially resolving capability of HCTFT 64
4.4 Feature of sensitivity enhancement in HCTFT 67
4.5 Effects of stress gate voltage 72
4.6 Evolution of HC degradation 74
4.7 Effects of post-metal Plasma treatment 80
4.8 Summary 84
5 Analysis of HC Degradation Under AC Operations Using HCTFTs 85
5.1 Introduction 85
5.2 Experimental setup 86
5.3 Results and discussion 88
5.3.1 Effects of frequency 88
5.3.2 Effects of rising and falling times 92
5.3.3 Temporal evolution under AC stressing 98
5.4 Summary 101
6 Effective Density-of-states Distributions for Hot-carrier Degradations in Poly-Si TFTs 103
6.1 Introduction 103
6.2 Experimental setup of density of states extraction using FEC method 104
6.2.1 Flat-band voltage determination 104
6.2.2 Relationship between current-voltage and surface band-bending 105
6.2.3 Density of states in terms of surface band-bending 106
6.2.4 Experimental setup for DOS extraction 107
6.3 Experimental setup of device simulation 109
6.4 Results and Discussion 110
6.4.1 Density of states before and after the hot-carrier stress 111
6.4.2 Temporal evolution of DOS during hot-carrier stressing 115
6.4.3 Recreating stressed IV characteristics using MTs 117
6.5 Summary 121
7 Conclusions and Future Prospects 123
7.1 Conclusions 123
7.2 Future Prospects 125
7.2.1 Mobility enhancement in nanowire TFTs 126
7.2.2 Applications for the proposed nanowire TFTs 127
7.2.3 Resolution enhancement in HCTFT 128
7.2.4 Hot-carrier degradation in p-channel TFTs 128
7.2.5 More bias conditions in AC stressing modes 128
References 131
Vita 157
Publication List 159

Chapter 1
[1.1] A. G. Lewis, I. -W. Wu, T. Y. Huang, A. Chiang, and R. H. Bruce, “Active matrix liquid crystal display design using low and high temperature processed polysilicon TFTs,” in IEDM Tech. Dig., 1990, pp. 843-846.
[1.2] M. G. Clark, “Current status and future prospects of poly-Si devices,” IEE Proceedings - Circuits, Devices and Systems, vol. 141, pp. 3-8, Feb. 1994.
[1.3] G. Fortunato, “Polycrystalline silicon thin-film transistors: A continuous evolving technology,” Thin Solid Films, vol. 296, pp. 82-90, Mar. 1997.
[1.4] S. H. Jung, W. J. Nam, J. H. Lee, J. H. Jeon, and M. K. Han, “A new low-power pMOS poly-Si inverter for AMDs,” IEEE Electron Device Lett., vol. 26, pp. 23-25, Jan. 2005.
[1.5] S. D. S. Malhi, H. Shichijo, S. K. Banerjee, R. Sundaresan, M. Elahy, G. P. Polack, W. F. Richardson, A. H. Shah, L. R. Hite, R. H. Womack, P. K. Chatterjee, and H. W. Lam, “Characteristics and three-dimensional integration of MOSFET’s in small-grain LPCVD polycrystalline silicon,” IEEE Trans. Electron Devices, vol. 32, pp. 258-281, Feb. 1985.
[1.6] T. Yamanaka, T. Hashimoto, N. Hasegawa, T. Tanaka, N. Hashimoto, A. Shimizu, N. Ohki, K. Ishibashi, K. Sasaki, T. Nishida, T. Mine, E. Takeda, and T. Nagano, “Advanced TFT SRAM cell technology using a phase-shift lithography,” IEEE Trans. Electron Devices, vol. 42, pp. 1305-1313, Jul. 1995.
[1.7] M. Aoki, T. Hashimoto, T. Yamanaka, and T. Nagano, “Large 1/f noise in polysilicon TFT loads and its effects on the stability of SRAM cells,” Jpn. J. Appl. Phys., vol. 35, pp. 838-841, Feb. 1996.
[1.8] S. Koyama, “A novel cell structure for giga-bit EPROMs and flash memories using polysilicon thin film transistors,” in VLSI Symp. Tech. Dig., 1992, pp. 44-45.
[1.9] N. D. Young, G. Harkin, R. M. Bunn, D. J. McCulloch, and I. D. French, “The fabrication and characterization of EEPROM arrays on glass using a low-temperature poly-Si TFT process,” in IEEE Trans. Electron Devices, vol. 43, pp. 1930-1936, Nov. 1996.
[1.10] T. Kaneko, Y. Hosokawa, M. Tadauchi, Y. Kita, and H. Andoh, “400 dpi integrated contact type linear image sensors with poly-Si TFTs analog readout circuits and dynamic shift registers,” IEEE Trans. Electron Devices, vol. 38, pp. 1086-1093, May, 1991.
[1.11] Y. Hayashi, H. Hayashi,M. Negishi, and T. Matsushita, “A thermal printer head with CMOS thin-film transistors and heating elements integrated on a chip,” in Proc. Int. Solid-State Circuit Conf., 1988, pp. 266-267.
[1.12] D. B. Meakin, P. A. Coxon, P. Migliorato, J. Stoemenos, and N. A. Economou, “High-performance thin-film transistors from optimized polycrystalline silicon films,” Appl. Phys. Lett., vol. 50, pp. 1894-1896, Jun. 1987.
[1.13] A. Mimura, N. Konishi, K. Ono, J. I. Ohwada, Y. Hosokawa, Y. A. Ono, T. Suzuki, K. Miyata, and H. Kawakami, “High performance low-temperature poly-Si n-channel TFTs for LCD,” IEEE Trans. Electron Devices, vol. 36, pp. 351-359, Feb. 1989.
[1.14] K. Sera, F. Okumura, H. Uchida, S. Itoh, S. Kaneko, and K. Hotta, “High-performance TFTs fabricated by XeCl excimer laser annealing of hydrogenated amorphous-silicon film,” IEEE Trans. Electron Devices, vol. 36, pp. 2868-2872, Dec. 1989.
[1.15] S. D. Brotherton, D. J. McCulloch, J. B. Clegg, and J. P. Gowers, “Excimer-laser-annealed poly-Si thin-film transistors,” IEEE Trans. Electron Devices, vol. 40, pp. 407-413, Feb. 1993.
[1.16] P. Mei, J. B. Boyce, M. Hack, R. A. Lujan, R. I. Johnson, G. B. Anderson, D. K. Fork, and S. E. Ready, “Laser dehydrogenation/crystallization of plasma-enhanced chemical vapor deposited amorphous silicon for hybrid thin film transistors,” Appl. Phys. Lett., vol. 64, pp. 1132-1134, Feb. 1994.
[1.17] T. Noguchi, A. J. Tang, J. A. Tsai, and R. Reif, “Comparison of effects between large-area-beam ELA and SPC on TFT characteristics,” IEEE Trans. Electron Devices, vol. 43, pp. 1454-1458, Sep. 1996.
[1.18] H. Kuriyama, S. Kiyama, S. Noguchi, T. Kuwahara, S. Ishida, T. Nohda, K. Sano, H. Iwata, S. Tsuda, S. Nakano, “High mobility poly-Si TFT by a new excimer laser annealing method for large area electronics,” in IEDM Tech. Dig., pp. 563-566, 1991.
[1.19] Z. Meng, M. X. Wang, and M. Wong, “High performance low temperature metal-induced unilaterally crystallized polycrystalline silicon thin film transistors for system-on-panel applications,” IEEE Trans. Electron Devices, vol. 47, pp. 404-409, Feb. 2000.
[1.20] G. Liu and S. J. Fonash, “Polycrystalline silicon thin film transistors on Corning 7059 glass substrates using short time, low-temperature processing,” Appl. Phys. Lett., vol. 62, pp. 2554-2556, May 1993.
[1.21] J. G. Fossum, A. Ortiz-Conde, H. Shichijo, S. K. Banerjee, “Anomalous leakage current in LPCVD polysilicon MOSFET's,” IEEE Trans. Electron Devices, vol. 32, pp. 1878-1884, Sep. 1985.
[1.22] I. W. Wu, T. Y. Huang, W. B. Jackson, A. G. Lewis, and A. Chiang, “Passivation kinetics of two types of defects in polysilicon TFT by plasma hydrogenation,” IEEE Electron Device Lett., vol. 12, pp. 181-183, Apr. 1991.
[1.23] T. F. Chen, C. F. Yeh, and J. C. Lou, “Investigation of grain boundary control in the drain junction on laser-crystalized poly-Si thin film transistors,” IEEE Electron Device Lett., vol. 24, pp. 457-459, Jul. 2003.
[1.24] S. Seki, O. Kogure, and B. Tsujiyama, “Leakage current characteristics of offset-gate-structure polycrystalline-silicon MOSFETs,” IEEE Electron Device Lett., vol. 8, pp. 434-436, Sep. 1987.
[1.25] K. Tanaka, H. Arai, and S. Kohda, “Characteristics of offset-structure polycrystalline-silicon thin-film transistors,” IEEE Electron Device Lett., vol. 9, pp. 23-25, Jan. 1988.
[1.26] C. A. Dimitriadis, G. Kamarinos, and J. Brini, “Leakage current of offset gate p- and n-channel excimer laser annealed polycrystalline silicon thin-film transistors,” Solid State Electron., vol. 45, pp. 365-368, Feb. 2001.
[1.27] K. Y. Choi, J. W. Lee, M. K. Han, “Gate-overlapped lightly doped drain poly-Si thin-film transistors for large area-AMLCD,” IEEE Trans. Electron Devices, vol.45, pp. 1272-1279, Jun. 1998.
[1.28] K. Tanaka, K. Nakazawa, S. Suyama, and K. Kato, “Characteristics of field-induced-drain (FID) poly-Si TFTs with high on/off current ratio,” IEEE Trans. Electron Devices, vol. 39, pp. 916-920, Apr. 1992.
[1.29] R. E. Proano, R. S. Misage, D. G. Ast, “Development and electrical properties of undoped polycrystalline silicon thin-film transistors,” IEEE Trans. Electron Devices, vol. 36, pp. 1915-1922, Sep. 1989.
[1.30] E. M. Vogel, “Technology and metrology of new electronic materials and devices,” Nature Nanotechnology, vol. 2, pp. 25-32, Jan. 2007.
[1.31] D. Hisamoto, W. C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T. J. King, J. Bokor, and C. M. Hu, “FinFET - a self-aligned double-gate MOSFET scalable to 20 nm,” IEEE Trans. Electron Devices, vol. 47, pp. 2320-2325, Dec. 2000.
[1.32] R. H. Chen, A. N. Korotkov, and K. K. Likharev, “Single-electron transistor logic,” Appl. Phys. Lett., vol. 68, pp. 1954-1956, Apr. 1996.
[1.33] S. W. Chung, J. Y. Yu, and J. R. Heath, “Silicon nanowire devices,” Appl. Phys. Lett., vol. 76, pp. 2068-2070, Apr. 2000.
[1.34] Y. Cui, Z. Zhong, D. Wang, W. U. Wang, and C. M. Lieber, “High performance silicon nanowire field effect transistors,” Nano Letters, vol. 3, pp. 149-152, Feb. 2003.
[1.35] H. Fujii, T. Matsukawa, S. Kanemaru, H. Yokoyama, and J. Itoh, “Characterization of electrical conduction in silicon nanowire by scanning Maxwell-stress microscopy,” Appl. Phys. Lett., vol. 78, pp. 2560-2562, Apr. 2001.
[1.36] S. Q. Lud, M. G. Nikolaides,I. Haase, M. Fischer, and A. R. Bausch, “Field effect of screened charges: Electrical detection of peptides and proteins by a thin-film resistor,” ChenPhysChem, vol. 7, pp. 379-384, 2006.
[1.37] H. T. Ng, J. Han, T. Yamada, P. Nguyen, Y. P. Chen, and M. Meyyappan, “Single crystal nanowire vertical surround-gate field-effect transistor,” Nano Letters, vol. 4, pp. 1247-1252, Jul. 2004.
[1.38] Y. Cui, Q. Wei, H. Park, and C. M. Lieber, “Nanowire nanosensors for highly sensitive and selective detection of biological and chemical species,” Science, vol. 293, pp. 1289-1292, Aug. 2001.
[1.39] Z. Li, Y. Chen, X. Li, T. I. Kamins, K. Nauka, and R. S. Williams, “Sequence-specific label-free DNAsensors based on silicon nanowires,” Nano Letters, vol. 4, pp. 245-247, Apr. 2004.
[1.40] L. Risch, L. Dreekornfeld, J. Hartwich, F. Hofmann, J. Kretz, and M. Stadele, “Multi gate transistors and memory cells for future CMOS generation,” in Tech. Dig. IEEE 2004 Silicon Nanoelectronics Workshop, pp. 1-2.
[1.41] J. E. Jang, S. N. Cha, Y. Choi, T. B. Butler, D. J. Kang, and D. G. Hasko et al., “Nanoelectromechanical DRAM for ultra-large-scale integration,” in IEDM Tech. Dig., 2005, pp. 269-272.
[1.42] C. A. Dimitriadis, P. A. Coxon, A. J. Lowe, J. Stoemenos, and N. A. Economou, “Control of the performance of polysilicon thin-film transistor by high-gate-voltage stress,” IEEE Electron Device Lett., vol. 12, pp. 676-678, Dec. 1991.
[1.43] N. D. Young and A. Gill, “Water-related instability in TFTs formed using deposited gate oxides,” Semicond. Sci. Technol., vol. 7, pp. 1103-1108, Aug. 1992.
[1.44] T. Yoshida, K. Yoshino, M. Takei, A. Hara, N. Sasaki and T. Tsuchiya, “Experimental evidence of grain-boundary related hot-carrier degradation mechanism in low-temperature poly-Si thin-film-transistors,” in IEDM Tech. Dig., 2003, pp. 8.8.1-8.8.4.
[1.45] A. T. Hatzopoulos, D. H. Tassis, N. A. Hastas, C. A. Dimitriadis and G. Kamarinos, “An analytical hot-carrier induced degradation model in polysilicon TFTs,” IEEE Trans. Electron Devices, vol. 52, pp. 2182-2187, Oct. 2005.
[1.46] N. Kato, T. Yamada, S. Yamada, T. Nakamura, and T. Hamano, “Degradation mechanism of polysilicon TFT’s under D.C. stress,” in IEDM Tech. Dig., 1992, pp. 677-680.
[1.47] S. Inoue, and H. Ohshima, “New degradation phenomenon in wide channel poly-Si TFTs fabricated by low temperature process,” in IEDM Tech. Dig., 1996, pp. 781-784.
[1.48] S. Ecoffey, M. Mazza, V. Pott, D. Bouvet, A. Schmid, and Y. Leblebici et al., “A new logic based on hybrid MOSFET-polysilicon nanowires,” in IEDM Tech. Dig., 2005, pp. 277-280.
[1.49] L. Risch, L. Dreekornfeld, J. Hartwich, F. Hofmann, J. Kretz, and M. Stadele, “Multi gate transistors and memory cells for future CMOS generation,” in Tech. Dig. IEEE 2004 Silicon Nanoelectronics Workshop, pp. 1-2.
[1.50] X. Duan and C. M. Lieber, “Laser-assisted catalytic growth of single crystal GaN nanowires,” J. of American Chemical Society, vol. 122, pp. 188-189, Jan. 2000.

Chapter 2
[2.1] F. L. Yang, D. H. Lee, H. Y. Chen, C. Y. Chang, S. D. Liu, and C. C. Huang et al., “5nm-gate nanowire FinFET,” in Tech. Dig. 2004 Symp. VLSI Technol., pp. 196-197.
[2.2] S. Ecoffey, M. Mazza, V. Pott, D. Bouvet, A. Schmid, and Y. Leblebici et al., “A new logic based on hybrid MOSFET-polysilicon nanowires,” in IEDM Tech. Dig., 2005, pp. 277-280.
[2.3] L. Risch, L. Dreekornfeld, J. Hartwich, F. Hofmann, J. Kretz, and M. Stadele, “Multi gate transistors and memory cells for future CMOS generation,” in Tech. Dig. IEEE 2004 Silicon Nanoelectronics Workshop, pp. 1-2.
[2.4] X. Duan, C. Niu, V. Sahi, J. Chen, J. W. Parce, S. Empedocles, and J. L. Goldman, “High-performance thin-film transistors using semiconductor nanowires and nanoribbons,” Nature, vol. 425, pp. 274-278, Sep. 2003.
[2.5] Y. Cui, Q. Wei, H. Park, and C. M. Lieber, “Nanowire nanosensors for highly sensitive and selective detection of biological and chemical species,” Science, vol. 293, pp. 1289-1292, Aug. 2001.
[2.6] Z. Li, Y. Chen, X. Li, T. I. Kamins, K. Nauka, and R. S. Williams, “Sequence-specific label-free DNA sensors based on silicon nanowires,” Nano Letters, vol. 4, pp. 245-247, Feb. 2004.
[2.7] J. E. Jang, S. N. Cha, Y. Choi, T. B. Butler, D. J. Kang, and D. G. Hasko et al., “Nanoelectromechanical DRAM for ultra-large-scale integration,” in IEDM Tech. Dig., 2005, pp. 269-272.
[2.8] Y. K. Choi, J. Zhu, J. Grunes, J. Bokor, and G. A. Somorjai, “Fabrication of sub-10-nm silicon nanowire arrays by size reduction lithography,” J. Phys. Chem. B, vol. 107, pp. 3340-3343, Apr. 2003.
[2.9] R. Lin, H. C. Lin, J. Y. Yang, S. W. Shen, and C. J. Su, “A novel method for the preparation of Si nanowires,” in Int’l Conf. on Solid State Devices and Materials, 2006, pp. 692-693.
[2.10] X. Duan and C. M. Lieber, “Laser-assisted catalytic growth of single crystal GaN nanowires,” J. of American Chemical Society, vol. 122, pp. 188-189, Jan. 2000.
[2.11] M. Paulose, O. K. Varghese, and C. A. Grimes, “Synthesis of gold-silica composite nanowires through solid-liquid-solid phase growth,” Journal of Nanoscience and Nanotechnology, vol. 3, pp. 341-346, Aug. 2003.
[2.12] A. Persson, M. W. Larsson, S. Senstrom, B. J. Ohlsson, L. Samulson and L. R. Wallenberg, “Solid-phase diffusion mechanism for GaAs nanowire growth,” Nature Materials, vol. 3, pp. 677-681, Oct. 2004.
[2.13] N. A. Sanford, L. H. Robins, M. H. Gray, Y.-S. Kang, J. E. Van Nostrand, C. Stutz, R. Cortez, A. V. Davydov, A. Shapiro, I. Levin, and A. Roshko, “Fabrication and analysis of GaN nanorods grown by MBE,” Physica Status Solidi C, vol. 2, no. 7, pp. 2357-2360, 2005.
[2.14] H. Y. Peng, X. T. Zhou, N. Wang, Y. F. Zheng, L. S. Liao, W. S. Shi, C. S. Lee and S. T. Lee, “Bulk-quantity GaN nanowires synthesized from hot filament chemical vapor deposition,” Chemical Physics Lett., vol. 327, pp. 263-270, Sep. 2000.
[2.15] J. Su, G. Cui, M. Gherasimova, H. Tsukamoto, J. Han, D. Ciuparu, S. Lim, L. Pfefferle, Y. He, A. V. Nurmikko, C. Broadbridge, and A. Lehman, “Catalytic growth of group III-nitride nanowires and nanostructures by metalorganic chemical vapor deposition,” Appl. Phys. Lett., vol. 86, pp. 013105-013107, Jan. 2005.
[2.16] Y. Huang, X. Duan, Q. Wei, and C. M. Lieber, “Directed assembly of one-dimensional nanostructures into functional networks,” Science, vol. 291, pp. 630-633, Jan. 2001.
[2.17] Y. Wu, Y. Cui, L. Huynh, C. J. Barrelet, D. C. Bell, and C. M. Lieber, “Controlled growth and structures of molecular-scale silicon Nanowires,” Nano Letters, vol. 4, pp. 433-436, Mar 2004.
[2.18] M. Cao, T. J. King, and K. C. Saraswat, “Determination of the densities of gap states in hydrogenated polycrystalline Si and Si0.8Ge0.2 films,” Appl. Phys. Lett., vol. 61, pp. 672-674, Aug. 1992.
[2.19] Y. J. Tung, X. Huang, T. J. King, J. Boyce, and J. Ho, “Improved DC reliability of polysilicon thin-film transistors with deuterium plasma treatment,” in SID Symp. Dig. of Tech. Papers, 1999, vol. 30, pp. 398-401
[2.20] M. -J. Tsai, F. -S. Wang, K. -L. Cheng, S. -Y. Wang, M. -S. Feng and H. -C. Cheng, “Characterization of H2/N2 plasma passivation process for poly-Si thin film transistors (TFTs),” Solid-State Electronics, vol. 38, pp. 1233-1238, Jun. 1995.
[2.21] H. -C. Cheng, F. -S. Wang, and C. -Y. Huang, “Effects of NH3 plasma passivation on n-channel polycrystalline silicon thin-film transistors,” IEEE Trans. Electron Devices, vol. 44, pp. 64-68, Jan. 1997.
[2.22] K. Y. Choi, J. S. Yoo, M. K. Han, and Y. S. Kim, “Hydrogen passivation on the grain boundary and intragranular defects in various polysilicon thin-film transistors,” Jpn. J. of Appl. Phys., vol. 35, pp. 915-918, Feb. 1996.
[2.23] H. Wang, M. Chan, S. Jagar, V. M. C. Poon, M. Qin, and Y. Wang et al., “Super thin-film transistor with SOI CMOS performance formed by a novel grain enhancement method,” IEEE Trans. Electron Devices, vol. 47, pp. 1580-1586, Aug. 2000.
[2.24] W. B. Jackson, N. M. Johnson, C. C. Tsai, I-W. Wu, A. Chiang, and D. Smith, “Hydrogen diffusion in polycrystalline silicon thin films,” Appl. Phys. Lett., vol. 61, pp. 1670-1672, Oct. 1992.
[2.25] H. Wang, M. Chan, Y. Wang, and P. K. Ko, “The behavior of narrow-width SOI MOSFET’s with MESA isolation,” IEEE Trans. Electron Devices, vol. 47, pp. 593-600, Mar 2000.
[2.26] Y. Cui, X. Duan, J. Hu, and C. M. Lieber, “Doping and electrical transport in silicon nanowires,” Journal of Physical Chemistry B, vol. 104, pp. 5213-5216, Jun. 2000.

Chapter 3
[3.1] P. Migliorato P, and D. B. Meakin, “Material properties and characteristics of polysilicon transistors for large area electronics,” Applied Surface Science, vol. 30, pp. 353-371, Oct. 1987.
[3.2] S. D. Brotherton, J. R. Ayres, and N. D. Young, “Characterization of low-temperature poly-Si thin-film transistors,” Solid-State Electronics, vol. 34, pp. 671-679, Jul. 1991.
[3.3] C. -F. Yeh, T. -Z. Yang, C. -L. Chen, T. -J. Chen and Y. -C. Yang, “Experimental comparison of off-state current between high-temperature- and low-temperature-processed undoped channel polysilicon thin-film transistors,” Jpn. J. of Appl. Phys., vol. 32, pp. 4472-4478, Oct. 1993.
[3.4] S. K. Madan and D. A. Antoniadis, “Leakage current mechanisms in hydrogen-passivated fine-grain polycrystalline silicon on insulator MOSFETs,” IEEE Trans. Electron Devices, vol.33, pp.1518-1528, Oct. 1986.
[3.5] A. Rodriguez, E. G. Moreno, H. Pattyn, J. F. Nijs, and R. P. Mertens, “Model for the anomalous off current of polysilicon thin film transistors and diodes,” IEEE Trans. Electron Devices, vol. 40, pp. 938-943, May 1993.
[3.6] O. K. B. Lui and P. Migliorato, “A new generation-recombination model for device simulation including the Poole-Frenkel effect and phonon-assisted tunneling,” Solid-State Electronics, vol. 41, pp. 575-583, Apr. 1997.
[3.7] I. -W. Wu, A. G. Lewis, T. Y. Huang, W. B. Jackson, and A. Chiang, “Mechanism and device-to-device variation of leakage current in polysilicon thin film transistors,” in IEDM Tech. Dig., 1990, pp. 867-870.
[3.8] K. Ono, T. Aoyama, N. Konishi, and K. Miyata, “Analysis of current voltage characteristics of low-temperature-processed polysilicon thin-film transistors,” IEEE Trans. Electron Devices, vol. 39, pp. 792-802, Apr. 1992.
[3.9] J.G. Fossum, A. Ortiz-Conde, H. Shichijo, and S. K. Banerjee, “Anomalous leakage current in LPCVD polysilicon MOSFET's,” IEEE Trans. Electron Devices, vol. 32, pp. 1878-1884, Sep. 1985.
[3.10] M. Yazaki, S. Takenaka, and H. Ohshima, “Conduction mechanism of leakage current observed in metal-oxide-semiconductor transistors and poly-Si thin-film transistors,” Jpn. J. of Appl. Phys., vol. 31, pp. 206-209, Feb. 1992.
[3.11] S. K. Madan, and D. A. Antoniadis, “Leakage current mechanisms in hydrogen-passivated fine-grain polycrystalline silicon on insulator MOSFET's,” IEEE Trans. Electron Devices, vol. 33, pp. 1518-1528, Oct. 1986.
[3.12] K. R. Olasupo and M. K. Hatalis, “Leakage current mechanism in sub-micron polysilicon thin-film transistors,” IEEE Trans., Electron Devices, vol.43, pp. 1218-1223, Aug. 1996.
[3.13] T. Y. Ihn, T. K. Kim, B. I. Lee, and S. K. Joo, “A study on the leakage current of poly-Si TFTs fabricated by metal induced lateral crystallization,” Microelectronics Reliability, vol.39, pp. 53-58, Jan. 1999.
[3.14] A. B. Y. Chan, C. T. Nguyen, P. K. Ko, M. Wong, A. Kumar, J. Sin, and S. S. Wong, “Optimizing polysilicon thin-film transistor performance with chemical-mechanical polishing and hydrogenation,” IEEE Electron Device Lett., vol. 17, pp. 518-520, Nov. 1996.
[3.15] G. P. Pollack, W. F. Richardson, S. D. S. Malhi, T. Bonifield, H. Shichijo, S. Banerjee, M. Elahy, A. H. Shah, R. Womack, and P. K. Chatterjee, “Hydrogen passivation of polysilicon MOSFET's from a plasma nitride source,” IEEE Electron Device Lett., vol. 5, pp. 468-470, Nov. 1984.
[3.16] L. K. Lam, D. L. Chen, and D. G. Ast, “Plasma nitride hydrogen source encapsulation method to hydrogenate polysilicon thin film transistors,” Electrochem. Solid-State Lett., vol. 2, pp. 140-142, Mar. 1999.
[3.17] M. Rodder, D. A. Antoniadis, F. Scholz, and A. Kalnitsky, “Effects of H+ implant dose and film deposition conditions on polycrystalline-Si MOSFET characteristics,” IEEE Electron Device Lett., vol. 8, pp. 27-29, Jan. 1987.
[3.18] C. Min, Z. Tiemin, K. C. Saraswat, and J. D. Plummer, “Study on hydrogenation of polysilicon thin film transistors by ion implantation,” IEEE Trans., Electron Devices, vol.42, pp. 1134-1140, Jun. 1995.
[3.19] I. -W. Wu, A. G. Lewis, T. Y. Huang, and A. Chiang, “Effects of trap-state density reduction by plasma hydrogenation in low-temperature polysilicon TFT,” IEEE Electron Device Lett., vol. 10, pp. 123-125, Mar. 1989.
[3.20] I. -W Wu, T. -Y. Huang, W. B. Jackson, A. G. Lewis, and A. Chiang, “Passivation kinetics of two types of defects in polysilicon TFT by plasma hydrogenation,” IEEE Electron Device Lett., vol. 4, pp. 181-183, Apr. 1991.
[3.21] M. -J. Tsai, F. -S. Wang, K. -L. Cheng, S. -Y. Wang, M. -S. Feng, and H. -C. Cheng, “Characterization of H2/N2 plasma passivation process for poly-Si thin film transistors (TFTs),” Solid-State Electronics, vol. 38, pp. 1233-1238, Jun. 1995.
[3.22] H. -C. Cheng, F. -S. Wang, and C. -Y. Huang, “Effects of NH3 plasma passivation on n-channel polycrystalline silicon thin-film transistors,” IEEE Trans. Electron Devices, vol. 44, pp. 64-68, Jan. 1997.
[3.23] C. T. Liu and K. H. Lee, “An experimental study on the short-channel effects in undergated polysilicon thin-film transistors with and without lightly doped drain structures,” IEEE Electron Device Lett., vol. 14, pp. 149-151, Mar. 1993.
[3.24] K. Tanaka, H. Arai, and S. Kohda, “Characteristics of offset-structure polycrystalline-silicon thin-film transistors,” IEEE Electron Device Lett., vol. 9, pp. 23-25, Jan. 1988.
[3.25] S. Seki, O. Kogure, and B. Tsujiyama, “Leakage current characteristics of offset-gate-structure polycrystalline-silicon MOSFETs,” IEEE Electron Device Lett., vol. 8, pp. 434-436, Sep. 1987.
[3.26] K. Y. Choi, J. W. Lee, and M. K. Han, “Gate-overlapped lightly doped drain poly-Si thin-film transistors for large area-AMLCD,” IEEE Trans. Electron Devices, vol.45, pp. 1272-1279, Jun. 1998.
[3.27] K. Tanaka, K. Nakazawa, S. Suyama, and K. Kato, “Characteristics of field-induced-drain (FID) poly-Si TFTs with high on/off current ratio,” IEEE Trans. Electron Devices, vol. 39, pp. 916-920, Apr. 1992.
[3.28] B. H. Min, C. M. Park, and M. K. Han, “A novel polysilicon thin-film transistor with a p-n-p structured gate electrode,” IEEE Electron Device Lett., vol. 17, pp. 560-562, Dec. 1996.
[3.29] K. W. Kim, K. S. Cho, and J. Jang, “A polycrystalline silicon thin-film transistor with a thin amorphous buffer,” IEEE Electron Device Lett., vol. 20, pp. 560-562, Nov. 1999.
[3.30] Z. Xiong, H. Liu, C. Zhu, and J. K. O. Sin, “Characteristics of high-k spacer offset-gated polysilicon TFTs,” IEEE Trans. Electron Devices, vol. 51, pp. 1304-1308, Aug. 2004.
[3.31] M.-C. Lee, S.-H. Jung, I.-H. Song, and M.-K. Han, “A new poly-Si TFT structure with air cavities at the gate-oxide edges,” IEEE Electron Device Lett., vol. 22, pp. 539-541, Nov. 2001.
[3.32] T. E. Chang, C. Huang, and T. Wang, “Mechanisms of interface trap-induced drain leakage current in off-state n-MOSFET's,” IEEE Trans. Electron Devices, vol. 42, pp. 738-743, Apr. 1995.
[3.33] M. Bonnel, N. Duhamel, M. Guendouz, L. Haji, B. Loisel, and P. Ruault, “Poly-Si thin-film transistors fabricated with rapid thermal annealed silicon films,” Jpn. J. of Appl. Phys., vol. 30, pp. L1924-L1926, Nov. 1991.
[3.34] M. Cao, T. -J. King, and K. C. Saraswat, “Determination of the densities of gap states in hydrogenated polycrystalline Si and Si0.8Ge0.2 films,” Appl. Phys. Lett., vol. 61, pp. 672-674, Aug. 1992.

Chapter 4
[4.1] T. H. Ning, “Hot-electron emission currents in n-channel IGFET's,” in IEDM Tech. Dig., 1997, pp. 144-147.
[4.2] P. E. Cottrell, R. R. Troutman, and T. H. Ning, “Hot-electron emission in n-channel IGFETs,” IEEE J. of Solid-State Circuits, vol. 14, pp. 442-455, Apr. 1979.
[4.3] E. Takeda and N. Suzuki, “An empirical model for device degradation due to hot-carrier injection,” IEEE Electron Device Lett., vol. 4, pp. 111-113, Arp. 1983.
[4.4] E. Takeda, H. Kume, Y. Nakagome, T. Makino, A. Shimizu, and S. Asai, “An As-P(n+-n-) double diffused drain MOSFET for VLSI's,” in IEEE Trans. Electron Devices, vol. 30, pp. 652-657, Jun. 1983.
[4.5] A. G. Lewis, I. -W. Wu, T. Y. Huang, A. Chiang, and R. H. Bruce, “Active matrix liquid crystal display design using low and high temperature processed polysilicon TFTs.” in IEDM Tech. Dig., 1990, pp.843-846.
[4.6] M. G. Clark, “Current status and future prospects of poly-Si devices,” IEE Proceedings - Circuits, Devices and Systems, vol. 141, pp. 3-8, Feb. 1994.
[4.7] G. Fortunato, “Polycrystalline silicon thin-film transistors: A continuous evolving technology,” Thin Solid Films, vol. 296, pp. 82-90, Mar. 1997.
[4.8] S. H. Jung, W. J. Nam, J. H. Lee, J. H. Jeon, and M. K. Han, “A new low-power pMOS poly-Si inverter for AMDs,” IEEE Electron Device Lett., vol. 26, pp. 23-25, Jan. 2005.
[4.9] Y. Uraoka, T. Hatayama, T. Fuyuki, T. Kawamura, and Y. Tsuchihashi, “Reliability of low temperature poly-silicon tfts under inverter operation,” IEEE Trans. Electron Devices, vol.48, pp.2370-2374, Oct. 2001.
[4.10] I. W. Wu, W. B. Jackson, T. Y. Huang, A. G. Lewis, and A. Chiang, “Mechanism of device degradation in n-channel and p-channel polysilicon TFTs by electrical stressing,” IEEE Electron Device Lett., vol. 11, pp. 167-169, Apr. 1990.
[4.11] T. Yoshida, K. Yoshino, M. Takei, A. Hara, N. Sasaki and T. Tsuchiya, “Experimental evidence of grain-boundary related hot-carrier degradation mechanism in low-temperature poly-Si thin-film-transistors,” in IEDM Tech. Dig., 2003, pp. 8.8.1-8.8.4.
[4.12] A. T. Hatzopoulos, D. H. Tassis, N. A. Hastas, C. A. Dimitriadis and G. Kamarinos, “An analytical hot-carrier induced degradation model in polysilicon TFTs,” IEEE Trans. Electron Devices, vol. 52, pp. 2182-2187, Oct. 2005.
[4.13] F. V. Farmakis, J. Brini, G. Kamarinos and C. A. Dimitriadis, “Anomalous turn-on voltage degradation during hot-carrier stress in polycrystalline silicon thin-film transistors,” IEEE Electron Device Lett., vol. 22, pp. 74-76, Feb. 2001.
[4.14] T. -F. Chen, C. -F. Yeh, and J. -C. Lou, “Effects of grain boundaries on performance and hot-carrier reliability of excimer-laser annealed polycrystalline silicon Thin film transistors,” J. of Appl. Phys., vol. 95, pp. 5788-5794, May 2004.
[4.15] K. C. Moon, J. -H. Lee, and M. -K. Han, “The study of hot-carrier stress on poly-Si TFT employing C–V measurement,” IEEE Trans. Electron Devices, vol. 52, pp. 512-517, Apr. 2005.
[4.16] Y. Uraoka, T. Hatayama, T. Fuyuki, T. Kawamura and Y. Tsuchhashi, “Analysis of hot carrier effects in low temperature poly-Si TFTs using device simulator,” in Proc. IEEE 2001 Int. Conference on Microelectronic Test Structures, vol. 14, pp.251-256.
[4.17] Y. Uraoka, N. Hirai, H. Yano, T. Hatayama, and T. Fuyuki, “Analysis of reliability in low temperature poly-Si thin film transistors using pico-second time resolved emission microscope,” in IEDM Tech. Dig., 2002, pp. 577-580.
[4.18] Y. Toyota, T. Shiba, and M. Ohkura, “A new model for device degradation in low-temperature n-channel polycrystalline silicon TFTs under AC stress,” IEEE Trans. Electron Devices, vol. 51, pp. 927-933, Jun. 2004.
[4.19] D.N. Kouvatsos and D. Davazoglou, “Gate/drain bias-induced degradation effects in TFTs fabricated in unhydrogenated SPC polycrystalline silicon films,” Thin Solid Films, vol. 426, pp. 250-257, Feb. 2003.
[4.20] M. Cao, T. J. King, and K. C. Saraswat, “Determination of the densities of gap states in hydrogenated polycrystalline Si and Si0.8Ge0.2 films,” Appl. Phys. Lett., vol. 61, pp. 672-674, Aug. 1992.
[4.21] Y. J. Tung, X. Huang, T. J. King, J. Boyce, and J. Ho, “Improved DC reliability of polysilicon thin-film transistors with deuterium plasma treatment,” in SID Symp. Dig. of Tech. Papers, 1999, vol. 30, pp. 398-401.
[4.22] M. -J. Tsai, F. -S. Wang, K. -L. Cheng, S. -Y. Wang, M. -S. Feng and H. -C. Cheng, “Characterization of H2/N2 plasma passivation process for poly-Si thin film transistors (TFTs),” Solid-State Electronics, vol. 38, pp. 1233-1238, Jun. 1995.
[4.23] H. -C. Cheng, F. -S. Wang, and C. -Y. Huang, “Effects of NH3 Plasma Passivation on N-Channel Polycrystalline Silicon Thin-Film Transistors,” IEEE Trans. Electron Devices, vol. 44, pp. 64-68, Jan. 1997..
[4.24] I. -W. Wu, A. G. Lewis, T. -Y. Huang, and A. Chiang, “Effects of trap-state density reduction by plasma hydrogenation in low-temperature polysilicon TFT,” IEEE Electron Device Lett., vol. 10, pp. 123-125, Mar. 1989.
[4.25] T. J. King, M. G. Hack, and I. W. Wu, “Effective density-of-states distributions for accurate modeling of polycrystalline-silicon thin-film transistors,” J. of Appl. Phys., vol. 75, pp. 908-913, Jan. 1994.
[4.26] K. Y. Choi, J. S. Yoo, M. K. Han, and Y. S. Kim, “Hydrogen passivation on the grain boundary and intragranular defects in various polysilicon thin-film transistors,” Jpn. J. of Appl. Phys., vol. 35, pp. 915-918, Feb. 1996.
[4.27] I. W. Wu, W. B. Jackson, T. Y. Huang, A. G. Lewis, and A. Chiang, “Mechanism of device degradation in n- and p-channel polysilicon TFT’s by electrical stressing,” IEEE Electron Device Lett., vol. 11, pp. 167-170, Apr. 1990.

Chapter 5
[5.1] S. Uchikoga, “Low-temperature polycrystalline silicon thin-film transistor technologies for system-on-glass displays,” MRS Bulletin, vol. 27, pp. 881-886, Nov. 2002.
[5.2] M. C. McAlpine, R. S. Friedman, S. Jin, K. H. Lin, W. U. Wang, and C. M. Lieber, “High-performance nanowire electronics and photonics on glass and plastic substrates,” Nano Lett., vol. 3, pp. 1531-1535, Nov. 2003
[5.3] J. R. Ayres, N. D. Young, “Hot-carrier effects in devices and circuits formed from Poly-Si,” IEE Proceedings - Circuits Devices and Systems, vol. 141, pp. 38-44, Feb. 1994.
[5.4] Y. Uraoka, K. Kitajima, H. Kirimura, H. Yano, T. Hatayama and T. Fuyuki, “Degradation in low-temperature poly-si thin film transistors depending on grain boundaries,” Jpn. J. of Appl. Phys., vol. 44, pp. 2895-2901, May 2005.
[5.5] Y. Uraoka, T. Hatayama, T. Fuyuki, T. kawamura, and Y. Tsuchihashi, “Reliability of high-frequency operation of low-temperature polysilicon thin film transistors under dynamic stress,” Jpn. J. of Appl. Phys., vol. 39, pp. L1209-L1212, Dec. 2000.
[5.6] Y. Uraoka, T. Hatayama, and T. Fuyushi, “Reliability evaluation method of low temperature poly-silicon TFTs using dynamic stress,” in IEEE Intl. Conf. on Microelectronic Test Structures, 2000, pp. 158-162.
[5.7] Y. Uraoka, T. Hatayama, T. Fuyushi, T. Kawamura, and T. Tsuchihashi, “Reliability of low temperature poly silicon tfts under inverter operation,” IEEE Trans. Electron Devices, vol. 48, pp. 2370-2374, Oct. 2001.
[5.8] Y. Uraoka, H. Yano, T. Hatayama, and T. Fuyuki, “Comprehensive study on reliability of low temperature poly-Si thin-film transistors under dynamic complimentary metal oxide semiconductor operations,” Jpn. J. of Appl. Phys., vol. 41, pp. L2414-L2418, Apr. 2002
[5.9] Y. Uraoka, N. Hirai, H. Yano, T. Hatayama, and T. Fuyuki, “Analysis of reliability in low temperature poly-Si thin film transistors using pico-second time resolved emission microscope,” in IEDM Tech. Dig., 2002, pp. 577-580.
[5.10] Y. Uraoka, N. Hirai, H. Yano, T. Hatayama, and T. Fuyushi, “New evaluation method of reliability of poly-Si thin film transistors using pico-second time-resolved emission microscope,” in IEEE Intl. Conf. on Microelectronic Test Structures, 2003, pp. 173-177.
[5.11] Y. Toyota, T. Shiba, and M. Ohkura, “A new model for device degradation in low-temperature n-channel polycrystalline silicon TFTs under AC stress,” IEEE Trans. Electron Devices, vol. 51, pp. 927-933, Jun. 2004.
[5.12] Y. Toyota, T. Shiba, and M. Ohkura, “Mechanism of device degradation under AC stress in low-temperature polycrystalline silicon TFTs,” in IEEE Intl. Reliability Phys. Symp., 2002, pp. 278-282.
[5.13] K. M. Chang, Y. H. Chung, and G. M. Lin, “Hot carrier induced degradation in the low temperature processed polycrystalline silicon thin film transistors using the dynamic stress,” Jpn. J. of Appl. Phys., vol. 41, pp. 1941-1946, Apr. 2002.

Chapter 6
[6.1] Y. Uraoka, T. Hatayama, T. Fuyuki, T. Kawamura, and Y. Tsuchihashi, “Reliability of low temperature poly-silicon TFTs under inverter operation,” IEEE Trans. Electron Devices, vol.48, pp.2370-2374, Oct. 2001.
[6.2] I. W. Wu, W. B. Jackson, T. Y. Huang, A. G. Lewis, and A. Chiang, “Mechanism of device degradation in n-channel and p-channel polysilicon TFTs by electrical stressing,” IEEE Electron Device Lett., vol. 11, pp. 167-169, Apr. 1990.
[6.3] Y. Jeong, D. Nagashima, H. Kuwano, T. Nouda, and H. Hamada, “Mechanisms of electrical stress-induced degradation in H2/plasma hydrogenated n- and p-channel polysilicon thin film transistors,” Jpn. J. of Appl. Phys., vol. 41, pp. 5042-5047, Aug. 2002.
[6.4] B. Doyle, M. Bourcerie, J. -C. Marchetaux, and A. Boudou, “Interface state creation and charge trapping in the medium-to-high gate voltage range (Vd/2 ≥ Vg ≥ Vd) during hot-carrier stressing of n-MOS transistors,” IEEE Trans. Electron Devices, vol. 37, pp. 744-754, Mar. 1990.
[6.5] T. Yoshida, K. Yoshino, M. Takei, A. Hara, N. Sasaki and T. Tsuchiya, “Experimental evidence of grain-boundary related hot-carrier degradation mechanism in low-temperature poly-Si thin-film-transistors,” in IEDM Tech. Dig., 2003, pp. 8.8.1-8.8.4.
[6.6] T. -F. Chen, C. -F. Yeh, and J. -C. Lou, “Effects of grain boundaries on performance and hot-carrier reliability of excimer-laser annealed polycrystalline silicon thin film transistors,” J. of Appl. Phys., vol. 95, pp. 5788-5794, May 2004.
[6.7] K. C. Moon, J. -H. Lee, and M. -K. Han, “The study of hot-carrier stress on poly-Si TFT employing C–V measurement,” IEEE Trans. Electron Devices, vol. 52, pp. 512-517, Apr. 2005.
[6.8] Y. Uraoka, T. Hatayama, T. Fuyuki, T. Kawamura and Y. Tsuchhashi, “Analysis of hot carrier effects in low temperature poly-Si TFTs using device simulator,” in Proc. IEEE 2001 Int. Conference on Microelectronic Test Structures, vol. 14, pp.251-256.
[6.9] A. T. Hatzopoulos, D. H. Tassis, N. A. Hastas, C. A. Dimitriadis and G. Kamarinos, “An analytical hot-carrier induced degradation model in polysilicon TFTs,” IEEE Trans. Electron Devices, vol. 52, pp. 2182-2187, Oct. 2005.
[6.10] Y. Uraoka, N. Hirai, H. Yano, T. Hatayama, and T. Fuyuki, “Analysis of reliability in low temperature poly-Si thin film transistors using pico-second time resolved emission microscope,” in IEDM Tech. Dig., 2002, pp. 577-580.
[6.11] W. B. Jackson, N. M. Johnson, and D. K. Biegelsen, “Density of gap states of silicon grain boundaries determined by optical absorption,” Appl. Phys. Lett., vol. 43, pp. 195-197, Jul. 1983.
[6.12] B. Faughnan, “Subthreshold model of a polycrystalline silicon thin-film field-effect transistor,” Appl. Phys. Lett., vol. 50, pp. 290-292, Feb. 1987.
[6.13] M. Cao, T. J. King, and K. C. Saraswat, “Determination of the densities of gap states in hydrogenated polycrystalline Si and Si0.8Ge0.2 films,” Appl. Phys. Lett., vol. 61, pp. 672-674, Aug. 1992.
[6.14] T. J. King, M. G. Hack, and I. W. Wu, “Effective density-of-states distributions for accurate modeling of polycrystalline-silicon thin-film transistors,” J. of Appl. Phys., vol. 75, pp. 908-913, Jan. 1994.
[6.15] G. Fortunato, D. B. Meakin, P. Migliorato, and P. G. Lecomber, “Field-effect analysis for the determination of gap-state density and Fermi-level temperature dependence in polycrystalline silicon,” Philos. Mag. B., vol. 57, pp. 573-586, May 1988.
[6.16] J. Werner and M. Peisl, “Exponential band tails in polycrystalline semiconductor-flims,” Phys. Review B, vol. 31 pp. 6881-6883, May 1985.
[6.17] H. Ikeda, “Evaluation of grain boundary trap states in polycrystalline-silicon thin-film transistors by mobility and capacitance measurements,” J. of Appl. Phys., vol. 91, pp. 4637-4645, Apr. 1992.
[6.18] J. R Ayres, “Characterization of trapping states in polycrystalline-silicon thin film transistors by deep level transient spectroscopy,” J. of Appl. Phys., vol. 74, pp. 1787-1792, Aug. 1993.
[6.19] T. Suzuki, Y. Osaka, and M. Hirose, “Theoretical interpretations of the gap state density determined from the field effect and capacitance-voltage characteristics of amorphous semiconductor,” Jpn. J. of Appl. Phys., vol. 21, pp. L159-L161, Mar. 1982.
[6.20] G. Fortunato and P. Migliorato, “Determination of gap state density in polycrystalline silicon by field-effect conductance,” Appl. Phys. Lett., vol. 49, pp. 1025-1027, Oct. 1986.
[6.21] R. L. Weisfield and D. A. Anderson, “An improved field-effect analysis for the determination of the pseudogap-state density in amorphous-semiconductors,” Philos. Mag. B., vol. 44, pp. 83-93, Jan. 1981.
[6.22] M. Hack and A. G. Lewis, “Physical models for degradation effects in polysilicon thin-film transistors,” IEEE Trans. Electron Devices, vol. 40, pp. 890-897, May 1993.
[6.23] C. A. Dimitriadis, M. Kimura, M. Miyasaka, S. Inoue, F. V. Farmakis, J. Brini, and G. Kamarinos, “Effect of grain boundaries on hot-carrier induced degradation in large grain polysilicon thin-film transistors,” Solid-State Electronics, vol. 44, pp. 2025-2051, Nov. 2000.
Chapter 7
[7.1] I. H. Song, C. H. Kim, S. H. Kang, W. J. Nam, and M. K. Han, “A new multi-channel dual-gate poly-Si TFT employing excimer laser annealing recrystallization on pre-patterned a-Si thin film,” in IEDM Tech. Dig., 2002, pp. 561-564.
[7.2] S. W. Lee, T. H. Ihn, and S. K. Joo, “Fabrication of high-mobility p-channel poly-Si thin film transistors by self-aligned metal-induced lateral crystallization,” IEEE Electron Device Lett., vol. 17, pp. 407-409, Aug. 1996.
[7.3] C. J. Su, H. C. Lin, and T. Y. Huang, “High performance TFTs with Si nanowire channels fabricated by metal-induced lateral crystallization,” IEEE Electron Device Lett., vol. 27, pp. 582-584, Jul. 2006.
[7.4] L. Mariucci, G. Fortunato, R. Carluccio, A. Pecora, S. Giovannini, F. Massussi, L. Colalongo and M. Valdinoci, “Determination of hot-carrier induced interface state density in polycrystalline silicon thin-film transistors,” J. Appl. Physics, vol.84, pp. 2341-2438, Aug. 1998.
[7.5] A.T. Hatzopoulos, D.H. Tassis, N.A. Hastas, C.A. Dimitriadis and G. Kamarinos, “An analytical hot-carrier induced degradation model in polysilicon TFTs,” IEEE Trans. Electron Devices, vol. 52, pp. 2182-2187, Oct. 2005.
[7.6] M. S. Rodder, and D. A. Antoniadis, “Hot-carrier effects in hydrogen-passivated p-channel polycrystalline-Si MOSFET's,” IEEE Trans. Electron Devices, vol. 34, pp. 1079-1083, May 1987.
[7.7] K. Y. Lee, Y. K. Fang, C. W. Chen, K. C. Huang, M. S. Liang, and S. G. Wuu SG, “The anomalous behavior of hydrogenated/unhydrogenated polysilicon thin-film transistors under electric stress,” IEEE Electron Device Lett., vol. 18, pp. 382-384, Aug. 1997.
[7.8] N. A. Hastas, C. A. Dimitriadis, J. Brini, and G. Kamarinos, “Hot-carrier-induced degradation in short p-channel nonhydrogenated polysilicon thin-film transistors,” IEEE Trans. Electron Devices, vol. 49, pp. 1552-1557, Sep. 2002.
[7.9] Y. Toyota, M. Matsumura, M. Hatano, T. Shiba, and M. Ohkura, “A new study on the degradation mechanism in low-temperature p-channel polycrystalline silicon TFTs under dynamic stress,” IEEE Trans. Electron Devices, vol. 53, pp. 2280-2286, Sep. 2006.
[7.10] T. N. Ruckmongathan, M. Govind, and G. Deepak, “Reducing power consumption in liquid-crystal displays,” IEEE Trans. Electron Devices, vol. 53, pp. 1559-1566, Jul. 2006.
[7.11] Y. Uraoka, T. Hatayama, T. Fuyushi, T. Kawamura, and T. Tsuchihashi, “Reliability of low temperature poly silicon TFTs under inverter operation,” IEEE Trans. Electron Devices, vol. 48, pp. 2370-2374, Oct. 2001.
[7.12] J. R. Ayres, N. D. Young, “Hot-carrier effects in devices and circuits formed from Poly-Si,” in IEE Proceedings - Circuits Devices and Systems, vol. 141, pp. 38-44, Feb. 1994.
[7.13] J. C. Wang, E. Olthof, and W. Metselaar, “Hot-carrier degradation analysis based on ring oscillators,” Microelectronics and Reliability, vol. 46, pp. 1858-1863, Sep.-Nov. 2006.