臺灣博碩士論文加值系統

隨著製程的進步，導線延遲取代了元件的延遲，逐漸主宰著系統的效率，並且在設計上成為一個非常關鍵的因素。然而，導線的延遲很難在早期的系統設計中預知，必須要等到佈局(floorplan)完成才可以有初步的分析。因此，在這份論文中，我們會介紹導線延遲所造成的潛在因素是如何引響系統的效能，並且重新評估一些具有同成果品質(Quality of Result)目標的舊有佈局方法。接著我們提出一個新的效能感知(Throughput-Aware)佈局方法，這個新的方法會動態考量一個對效能最具關鍵的迴路集合，此迴路集合的元素還會隨著佈局的過程而改變，以達到增進系統效能(system throughput)的目標。實驗結果也顯示出我們的方法可大幅增進系統效能，有些例子裡甚至可以比以往的方法達到兩倍以上的成長。我們另外推薦一個整體設計流程，可以在系統設計步驟時就預估佈局對效能的影響，避免未來因為效能不足而造成冗長且高價的重複設計代價。

The wire delay is gradually dominating the system performance and becoming one of the most critical design issues. However, it is hard to precisely estimate the wire delay in early design stages until floorplan is actually done. In this thesis, we first show how the latency incurred by wire delay dominates system throughput and re-evaluate several exiting floorplanning strategies which are considered providing the same quality of result (QoR) in the past. Then we propose a new throughput-aware floorplanning strategy which dynamically optimizes a set of most critical performance cycles in the system. The experimental results show that our approach can even double the system performance than the previous method in certain cases. We also recommend a design flow that considers the floorplanning impact as early as the system-level design stage to avoid lengthy and costly redesign iterations.

1 Introduction─1
1.1 Motivation─4
1.2 Our Contribution─5
1.3 Organization of This Thesis─5
2 Preliminaries─6
2.1 System Throughput─6
2.2 The Effect of Floorplanning to Throughput─10
2.3 Problem Formulation─11
2.4 Related Works─12
2.4.1 The Modified SA-based Adjacent Constraint Graph (ACG) Floorplaner[14]─12
2.4.2The SA-based Floorplaner with Correlative Cost Function[9]─14
3 Throughput-Aware Floorplanning by Dynamically Considering
Multiple Critical Cycles ─16
3.1 The Consideration of Multiple Critical Cycles─16
3.2 Dynamic Cycle Set CTp─18
3.3 The SA-based Flow of Our Approach─20
4 Experimental Results─22
4.1 Environment Setup and Benchmarks─22
4.2 Weight Assignment─23
4.3 Results─23
4.3.1 Experiment I─23
4.3.2 Experiment II─25
4.4 Stability─26
4.5 Discussion─28
5 Throughput-Aware Design Flow─29
6 Conclusion─32
Reference─33
Appendix─35

[1] I International Technology Roadmap for Semiconductors, Semiconductor Industry Association, 2003.
[2] D. Matzke, “Will physical scalability sabotage performance gains?” IEEE Computer, vol. 30, pp. 37-39, 1997.
[3] D. M. Chapiro, “Globally-asynchronous locally-synchronous systems,” Ph.D. dissertation, Stanford Univ., CA, 1984.
[4] D. S. Bormann and P. Y. Cheung, “Asynchronous wrapper for heterogeneous systems,” in Proc. ICCD, pp.307-314, 1997.
[5] J. Muttersbach, T. Villiger and W. Fichtner, “Practical design of globally-asynchronous locally-synchronous systems,” in Proc. ASYNC, pp. 52-59, 2000.
[6] L. P. Carloni, K. L. McMillan, A. Saldanha and A. L. Sangiovanni-Vincentelli, “A methodology for “Correct-by-construction latency insensitive design,” in Proc. ICCAD, pp. 309-315, 1999.
[7] L. P. Carloni and A. L. Sangiovanni-Vincentelli, “Performance analysis and optimization of latency insensitive protocols,” in Proc. DAC, pp. 21-26, 2001.
[8] R. Lu and C. Koh, “Performance optimization of latency insensitive systems through buffer queue sizing of communication channels,” in Proc. ICCAD, pp. 227, 2003.
[9] S. Kumar, A. Jantsch, J-P. Soininen, M. Forsell, M. Millberg, J. Oberg, K. Tiensyrja, and A. Hemani, “A network on chip architecture and design methodology” in Proc. Symposium on VLSI, pp. 117-124, 2002.
[10] A. Hemani, A. Jantsch, S. Kumar, A. Postula, J. �鉉erg, M. Millberg, and D. Lindqvist, “Network on a chip: an architecture for billion transistor era,” in Proc. of the IEEE NorChip Conf., 2002
[11] M. R. Casu and L. Macchiarulo, “Floorplanning for throughput,” in Proc. ISPD, pp. 62-69, 2004.
[12] M. R. Casu and L. Macchiarulo, “Throughput-driven floorplanning with wire pipelining,” in IEEE Tran. CAD, vol. 24, pp. 663-675, 2005.
[13] M. R. Casu and L. Macchiarulo, “Floorplan assisted data rate enhancement through wire pipelining: a real assessment,” in Proc. ISPD, pp. 121-128, 2005.
[14] J. Wang, H. Zhou and P. Wu, “Processing rate optimization by sequential system floorplanning,” in Proc. ISQED, pp. 340-345, 2006.
[15] H. Zhou and J. Wang, “ACG-adjacent constraint graph for general floorplans,” in Proc. ICCD, pp. 572-575, 2004.
[16] R. Lu and C. Koh, “Performance analysis and efficient implementation of latency insensitive systems,” ECE technical report, Purdue Univ., IN, 2003.
[17] D. F. Wong and C. L. Liu, “A new algorithm for floorplan design,” in Proc. DAC, pp. 101-107, 1986.
[18] V. Agarwal, M.S. Hrishikesh, S.W. Keckler, and D. Burger, “Clock rate vs IPC: the end of the road for conventional microarchitectures,” in Proc. ISCA, pp. 248-259, 2000.