臺灣博碩士論文加值系統

隨著金氧半場效電晶體尺寸的微縮，傳統的閘極介電質-二氧化矽-厚度微縮到1到1.5奈米時，大量的漏電流將會從介電層直接穿遂過去，嚴重傷害到電晶體的可靠度與特性，因此利用高介電常數介電質來取代傳統的二氧化矽是勢在必行的。因為高介電常數介電質在與二氧化矽相等的等效厚度下，有較厚的實際介電層，故可以抵擋大量的直接穿遂電流。然而，在高介電常數的介電質中所產生的遷移率衰減與臨界電壓的不穩定都是其主要的存在問題。所以提昇驅動電流大小並且了解高電藉常數介電質導致的可靠度下降問題都是本研究主要的探討重點。
本論文首先探討氧化鋁鉿應用在堆疊式閘極N型金氧半場效電晶體下的特性。經由電壓-電流與電壓-電容等圖來萃取此高介常數介電質的等效厚度。另一部分，實驗中使用電漿增強式化學氣相沉積之氮化矽層，沉積在二氧化鉿與氧化鋁鉿的金氧半場效電晶體上，利用較厚的氮化矽厚度會產生較大的伸張應力現象發現N型金氧半場效電晶體之驅動電流隨著氮化矽厚度增加而增大。接著，我們也探討，二氧化鉿高介電常數介電質材料具伸張應變通道的金氧半場效電晶體，其定電壓應力的可靠度特性分析以及偏壓變溫不穩定特性(BTI)。發現雖然較厚的氮化矽厚度可以提升N型金氧半場效電晶體的驅動電流，但定電壓應力、偏壓變溫不穩定特性卻在覆蓋較厚的氮化矽之電晶體下更為嚴重。特別是在高溫條件下，氮化矽層造成的區域應力導致較多的介面狀態產生，這可能是由於通道內的應能量造成大量矽氫鍵結斷裂。

As the conventional SiO2-based gate insulator scales down to 1.0nm~1.5nm, a large direct tunneling current generates through ultra-thin oxide which cause a serious degradation in reliability and performance of device. Utilizing high-k dielectric to replace SiO2-based gate as an insulator to eliminate high leakage current is necessary due to its larger physical thickness under the same equivalent oxide thickness. However, mobility degradation and threshold voltage instability are the mainly concern. Therefore, enhance mobility while keeping low leakage current is our aim to realize. Beside, the reliability discussion for high-k dielectric needs to be understood.
In this thesis, the electrical characteristics of HfAlO/SiON gate stack of nMOSFET is discussed first. We extract the equivalent oxide thickness of HfAlO by capacitance-voltage curve and we carried out with capping SiN layer on HfAlO/SiON and HfAlO/SiON gate stack. The SiN film deposited by PECVD is used to induce tensile strain locally in the channel region. Driving currents on nMOSFETs devices are enhanced as the thickness of SiN layer increases due to increasing tensile strain in the channel region. Constant voltage stress (CVS) and bias temperature (BTI) characteristics of nMOSFET with tensile strain in the channel region are also discussed. We can find that the nMOSFETs devices with thicken SiN capping layer enhances drive current, the reliability concerns on CVS and BTI become huger when thicken SiN capping layer deposited. More interface states are generated in high CVS of nMOSFET with thicken SiN capping layer. This expresses that a higher amount of hydrogen incorporated during SiN capping layer deposition as well as the high strain energy stored in the channel.

Chapter 1 Introduction
1-1 Background and Motivation……………………………………………………1
1-2 Organization of the Thesis……………………………………………………...4
Chapter 2 Device fabrication and Measurement Setup
2-1 Experimental…………………………………………………………………...6.
2-2 Measurement Setup……………………………………………………………..8
Chapter 3 Electrical Characteristics of nMOSFETs with
HfAlO/SiON gate stack
3-1 Introduction……………………………………………………………………18
3-2 Brief Review of Strained Si……………………………………………………20
3-3 Electrical Characteristics of MOSFETs with different thickness of SiN capping
layer………………………………………………….......................................24
3-4 Summary……………………………………………………………………....30
Chapter 4 Reliability of MOSFETs with HfO2/SiON
4-1 Introduction……………………………………………………………………55
4-2 Brief Review of NBTI………………………………….………………………57
4-3 Reliability of MOSFETs with different thickness of SiN capping layer……… 61
4-4 Summary………………………………………………………………………65

Chapter 5 Conclusion and Future Work
5-1 Conclusion…………………………………………………………..…….…..79
5-2 Future Work……………………………………………………………………81

Reference
[1] M. Schulz, Nature (London) 399 (1999) 729-730
[2] B. H. Lee, A. Mocuta, S. Bedell, H. Chen, D. Sadana, K. Rim, P. O'Neil, R. Mo, K. Chan, C. Cabral, C. Lavoie, D. Mocuta, A. Chakravarti, R. M. Mitchell, J. Mezzapelle, F. Jamin, M. Sendelbach, H. Kermel, M. Gribelyuk, A. Domenicucci, K. A. Jenkins, S. Narasimha, S. H. Ku, M. Ieong, I. Y. Yang, E. Leobandung, P. Agnello, W. Haensch, and J. Welser, “Performance enhancement on sub-70nm strained silicon SOI MOSFETs on ultra-thin thermally mixed strained silicon/SiGe on insulator (TM-SGOI) substrate with raised S/D”, IEDM Tech. Dig., pp.946-948, December 2002.
[3] S. Takagi, T. Mizuno, T. Tezuka, N. Sugiyama, T. Numata, K. Usuda, Y. Moriyama, S. Nakaharai, J. Koga, A. Tanabe, N. Hirashita, and T. Maeda, “Channel structure design, fabrication and carrier transport properties of strained-Si/SiGe-on-insulator (strained-SOI) MOSFETs”, IEDM Tech. Dig., pp. 57-60, December 2003
[4] K. Rim, K. Chan, L. Shi, D. Boyd, J. Ott, N. Klymko, F. Cardone, L. Tai, S. Koester, M. Cobb, D. Canaperi, B. To, E. Duch, I. Babich, R. Carruthers, P. Saunders, G. Walker, Y. Zhang, M. Steen, and M. Ieong, “Fabrication and mobility characteristics of ultra-thin strained Si directly on insulator (SSDOI) MOSFETs”, IEDM Tech. Dig., pp.47-52, December 2003.
[5] T. Mizuno, N. Sugiyama, T. Tezuka, T. Numata, T. Maeda, and S. Takagi, “Design for scaled thin film strained-SOI CMOS devices with higher carrier mobility”, IEDM Tech. Dig., pp.31-34, December 2002.
[6]
[7] M. Y. Ho., H. Gong, G. D. Wilk, B. W. Busch, M.L. Green, W. H. Lin, A. See, S. K. Lahiri, M. E. Loomans, P. I. Raisanen, and T. Gustafsson, Appl. Phys. Lett81, pp.4218, 2002
[8] A. Callegari, E. Cartier, M. Gribelyuk, H. F. Okorn-Schmidt, and T. Zabel, J. Appl. Phys., vol.90, no. 12, p. 6466 (2001)
[9] E. P. Guseri, D. A. Buchanai, E. Cartier, et al., IEDM Tech. Dig., pp.223 (2000)
[10] V. Chan, R. Rengarajan, N. Rovedo, W. Jin, T. Hook, P. Nguyen, J. Chen, E. Nowak, X. Chen, D. Lea, A. Chakravarti, V. Ku, S. Yang, A. Steegen, C.Baiocco, P. Shafer, H. Ng, S. Huang, and C. Wann, “High speed 45 nm gate length MOSFETs integrated into a 90 nm bulk technology incorporating strain engineering,” in Tech. Dig. IEEE Int. Electron Devices Meeting, 2003, pp. 77–80.
[11] P.R. Chidambaram, B.A. Smith, L.H Hall, H. Bu, S. Chakravarthi, Y.Kim, A.V.
Samoilov, A.T. Kim, P.J. Jones, R.B. Irwin, M.J Kim, A.L.P Rotondaro, C.F Machala, and D.T. Grider, “35% drive current improvement from recessed-SiGe drain extensions on 37 nm gate length PMOS,” in Proc. Symp. VLSI Technology, 2004, pp. 48–49.
[12] S.E. Thompson, M. Armstrong, C. Auth, S. Cea, R. Chau, G. Glass, T. Hoffman,
J. Klaus, Ma Zhiyong, B. Mcintyre, A. Murthy, B. Obradovic, L. Shifren, S. Sivakumar, S. Tyagi, T. Ghani, K. Mistry, M. Bohr, and Y. El- Mansy,“A logic nanotechnology featuring strained silicon,” IEEE Electron Device Lett., vol. 25, pp. 191–193, Apr. 2004.
[13] S.-i. Takagi, J.L. Hoyt, J. Welser, and J.F. Gibbons, “Comparative study, of phonon limited mobility of two-dimensional electrons in strained and unstrained Si metal-oxide-semiconductor field-effect transistors,” J. Appl. Phys., vol. 80, no. 3, pp. 1567–1577, Aug. 1996.

[14] Haizhou Yin, K. D. Hobart, Rebecca L. Peterson, F. J. Kub, S. R. Shieh, T. S. Duffy, and J. C. Sturm, “Fully-depleted Strained-Si on Insulator NMOSFETs without Relaxed SiGE Buffers,” IEDM Tech. Dig., pp. 53-56 2003.59
[15] Issac Lauer, T. A. Langdo, Z. –Y. Cheng, J. G. Fiorenza, G. Breithwaite, M. T. Currie, C. W. Leitz, A. Lochtefeld, H. Badawi. M. T. Bulsara, M. Somerville, and D. A. Antoniadis, Fellow, IEEE, “Fully Depleted n-MOSFETs on Supercritical Thickness Strained SOI,” IEEE Electron Device Lett., vol. 25, pp. 83-85, Feb. 2004.
[16] K. Rim, K. Chan, L. Shi, D. Boyd, J. Ott, N. Klymko, F. Cardone, L. Tai, S. Koester, M. Cobb, D. Canaperi, B. To, E. Duch, I. Babich, R. Carruthers, P. Saunders, G. Walker, Y. Zhang, M. Steen, and M. Ieong, “Fabrication and Mobility Characteristics of Untra-thin Strained Si Directly on Insulator (SSDOI) MOSFETs,” IEDM Tech. Dig., 2003.
[17] J. R. Hwang, J. H. Ho,S.M. Ting, T.P. Chen, Y. Y. Hsieh, C. C. Huang, Y. Y. Chiang, H. K. Lee, Ariel Liu, T.M. Shen, G. Braithwaite, M. Currie, N, Gerrish, R. Hammond, A. Lochtefeld, F. Singaporewala, M. Bulsara, Q. Xiang, M. R. Lin, W. T. Shiau, Y. T. Loh, J. K. Chen, S. C. Chien, and Frank Wen, “Performance of 70nm Strained-Silicon CMOS Devices,” VLSI Symp. Tech. Dig., pp. 103-104,
2003.
[18] S. Ito, H. Namba, K. Yamaguchi, T. Hirata, K. Ando, S. Koyama, S. Kuroki, N.
Ikezawa, T. Suzuki, T. Saitoh, and T. Horiuchi, “Mechanical stress effect of etch-stop Nitride and its impact on deep submicron transistor design”, in IEDM Tech. Dig., pp.247-250, December 2000.
[19] A. Shimizu, K. Hachimine, N. Ohki, H. Ohta, M. Koguchi, Y. Nonaka, H. Sato,
and F. Ootsuka, “Local mechanical-stress control (LMC): A new technique for CMOS-performance enhancement”, in IEDM Tech. Dig., pp.433-436, 2001
[20] G. Scott, J. Lutze, M. Rubin, F. Nouri, and M. Manley, “NMOS Drive current reduction caused by transistor layout and trench isolation induced stress”, in IEDM Tech. Dig., pp.827-830, December 1999.
[21] T. Matsumoto, S. Maeda, H. Dang, T. Uchida, K. Ota, Y. Hirano, H. Sayama, T. Iwamatsu, T. Ipposhi, H. Oda, S. Maegawa, Y. Inoue, and T. Nishimura, “Novel SOI wafer engineering using low stress and high mobility CMOSFET with <100>-channel for embedded RF/Analog applications,” in IEDM Tech. Dig., pp.663-666, December 2002.
[22] T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, “A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors”, in IEDM Tech. Dig., pp.978-980, December 2003.
[23] A. Steegen, M. Stucchi, A. Lauwers, and K. Maex, “Silicide induced pattern density and orientation dependent transconductance in MOS transistors”, in IEDM Tech. Dig., pp.497-500, December 1999.
[24] S. Maikap, M. H. Liao, F. Yuan, M. H. Lee, C. Huang, S. T. Chang, and C. W. Liu, ”Package-strain-enhanced device and circuit performance”, in IEDM Tech. Dig., pp.233-236, December 2004.
[25] F. Ootsuka, S. Wakahara, K. Ichinose, A. Honzawa, S. Wada, H. Sato, T. Ando, H. Ohta, K. Watanabe, and T. Onai, “A highly dense, high-performance 130nm node CMOS technology for large scale system-on-a-chip applications”, IEDM Tech. Dig., pp.575-578, December 2000.
[26] S. Ito, H. Namba, K. Yamaguchi, T. Hirata, K. Ando, S. Koyama, S. Kuroki, N. Ikezawa, T. Suzuki, T. Saitoh, and T. Horiuchi, “Mechanical stress effect of etch-stop Nitride and its impact on deep submicron transistor design”, IEDM Tech. Dig., pp.247-250, December 2000.
[27] T.Ghani et al., IEDM Tech. Dig., pp.978-980. 2003.
[28] C. Zhi-Yuan, M.T. Currie, C.W. Leitz, G. Taraschi, E.A. Fitzgerald, J.L. Hoyt, and D.A. Antoniadis, “Electron mobility enhancement in strained-Si n-MOSFETs fabricated on SiGe-on-insulator (SGOI) substrates,” IEEE Electron Device Lett., vol. 22, pp. 321–323, July 2001.
[29] Mobility enhancement
[30] M. V. Fischetti, Z. Ren , P. M. Solomon, M. Yang, and K. Rim, “Six-band k•p calculation of the hole mobility in silicon inversion layers: Dependence on surface orientation, strain, and silicon thickness”, J. Appl. phys., vol.94, pp.1079-1095, 2003.
[31] T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, “A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors,” in Tech. Dig. IEEE Int. Electron Devices Meeting, 2003, pp. 11.6.1–11.6.3.
[32] M.D. Giles, M. Armstrong, C. Auth, S.M. Cea, T. Ghani, T. Hoffmann, R. Kotlyar, P. Matagne, K. Mistry, R. Nagisetty, B. Obradovic, R. Shaheed, L. Shifren, M. Stettler, S. Tyagi, X. Wang, C. Weber, and K. Zawadzki, “Understanding stress enhanced performance in Intel 90 nm technology,” in Proc. Symp. VLSI Technology, 2004, p. 118.
[33] J.-S. Goo, Q. Xiang, Y. Takamura, F. Arasnia, E. N. Paton, P. Besser, J. Pan, and M. Lin, “Band offset induced threshold variation in strained-Si nMOSFETs”, IEEE Electron Device Lett., vol. 24, pp.568-570, September 2003.
[34] S. E. Thompson, G. Sun, K. Wu, J. Kim, and T. Nishida, “Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs”, in IEDM Tech. Dig., pp.221-224, December 2004.
[35] W. Zhao, J. He, R. E. Belford, L. Wernersson, and A. Seabaugh, “Partially depleted SOI MOSFETs under uniaxial tensile strain”, IEEE Trans. Electron Devices, vol. 51, pp.317-323, March 2004.
[36] W. Mizubayashi, N. Yasuda, H. Ota, H. Hisamatsu, K. Tominaga, K. Iwamoto, K. Yamamoto, T. Horikawa, T. Nabatame, and A. Toriumi, “Carrier separation analysis for clarifying leakage mechanism in unstressed and stress HfAlOx/SiO2 stack dielectric layers,” IEEE Reliability Physics Symposium, pp. 188-193, 2004.
[37] M. Houssa, M. Naili, V. V. Afanas’ev, M. M. Heyns, and A. Stesmans, “Electrical and Physical Characterization of High-K Dielectric Layers,” in Tech. Dig. Symp. on VLSI Technology, pp. 196-199, 2001
[38] T. King, J. R. Pfiester, and K. C. Saraswat, “A variable-work-function polycrystalline-Si1-xGex gate material for submicrometer CMOS technologies”, IEEE Electron Device Lett., vol. 12, pp. 533 - 535, October 1991.
[39] T. Sadoh, Fitrianto, A. Kenjo, A. Miyauchi, H. Inoue and M. Miyao, “Mechanism of Improved Thermal Stability of B in Poly-SiGe Gate on SiON”, Jpn. J. Appl. Phys. vol. 41, pp.2468, 2002
[40] T. Aoyama, K. Suzuki, H. Tashiro, Y. Tada, and H. Arimoto, “Flat-band voltage shifts in P-MOS devices caused by carrier activation in P+-polycrystalline silicon and boron penetration”, in IEDM Tech. Dig., pp.627-630, December 1997.
[41] H. P. Tuinhout, A. H. Montree, J. Schmitz, and P. A. Stolk, “Effects of gate depletion and boron penetration on matching of deep submicron CMOS transistors”, in IEDM Tech. Dig., pp.631-634, December 1997.
[42] T. King, J. R. Pfiester, J. D. Shott, J. P. McVittie, and K. C. Saraswat, “A polycrystalline-Si1-xGex-gate CMOS technology”, in IEDM Tech. Dig., pp.253-256, December 1990.
[43] V. Z. Li, M. R. Mirabedini, R. T. Kuehn, J. J. Wortman, and M. C. Öztürk, “Single gate 0.15µm CMOS devices fabricated using RTCVD in-situ boron doped Si1-xGex gates”, in IEDM Tech. Dig., pp.833-836, December 1997.
[44] C. Salm, D. T. van Veen, D. J. Gravesteijn, J. Holleman, and P. H. Woerlee, “Diffusion and electrical properties of boron and arsenic doped poly-Si and poly-GexSi1–x (x ~ 0.3) as gate material for Sub-0.25 µm complementary metal oxide semiconductor applications”, J. Electrochem. Soc., vol.144, pp.3665–3673, 1997
[45] B. E. Deal, M. Sklar, A. S. Grove, and E. H. Snow, J. Electrochem. Soc.114, 266
~1967!.
[46] D.Frohman-Bentchkowsky, “A fully decoded 2048-bit electrically programmable
FAMOS read-only memory”, IEEE J Solid-State Circuits, vol.6, pp.301-306,
October 1971
[47] N.Sano,M. Tomizawa, A. Yoshii,”Temperature dependence of hot carrier effects in short-channel Si-MOSFETs’ in IEEE Transactions on Electron Devices, vol 42 , no 12, 1995, pp.2211-2216
[48] M.F. Lu, S. Chiang, A. Liu, S. H. Lu, M. S. Yeh, J. R. Hwang, T.H. Tang, W.T. Shiau, M. C. Chen and T. Wang, “Hot carrier degradation in novel strained-Si nMOSFETs”, in Proc. Int. Reliability Physics Symp.,pp 18-22, 2004
[49] IEEE Electron Device Lett., Vol 23, pp. 98-99, Feb 2002
[50] IEDM Tech. Dig.. pp. 19-22, 2000.