臺灣博碩士論文加值系統

本篇論文之重點在於利用蒙地卡羅模擬，來分析一種新產生的寫入干擾模式。為了節省元件面積，近年NOR型態的SONOS元件採用潛擴散式的位元線技術(Buried Diffusion Bit-lines)製作，其操作方式為熱電子寫入(CHEI)與熱電洞抹除(BTBHH)。而在元件尺寸越來越縮小之後，在此種元件寫入的過程中，發現鄰近的元件也同時會被寫入，形成干擾。此一干擾的原因為熱電子寫入的同時產生的二次熱電子，透過蒙地卡羅模擬，也得到了與實驗趨勢相符的結果。最後，針對元件尺寸繼續縮小對此一寫入干擾的影響也有所評估。

This thesis is focused on a new program disturb in a two-bit storage buried diffusion bit-line SONOS flash memory. In a NOR-type SONOS flash memory, channel hot electron program and band-to-band hot hole erase are usually employed. In channel hot electron program operation, channel hot electrons will cause impact ionizations. Generated holes from impact ionizations will be accelerated by the drain-to-substrate voltage and cause second impact ionization. The second impact ionization generated electrons, referred to as secondary electrons, may flow to a neighboring cell and cause a program disturb. In this thesis, a multi-step Monte Carlo simulation is used to explore this mechanism for it can accurately obtain the high energy tail of the secondary electron distribution function. Both electron and hole Monte Carlo simulations in this thesis include a full-band structure. In addition, the effects of substrate bias, bit-line dimension and pocket implant on the program disturb will be characterized and evaluated by a Monte Carlo simulation.

Chinese Abstract i
English Abstract ii
Acknowledgements iii
Contents iv
Figure Captions vi
Chapter 1 Introduction 1
Chapter 2 Array Structure and Operations of SONOS Flash Memory 3
2.1 Introduction 3
2.2 Buried Diffusion Bit-Line SONOS Memory 3
2.3 Operation Modes 3
Chapter 3 New Program Disturb in a SONOS Array 7
3.1 Introduction 7
3.2 Channel Initiated Secondary Electron Programming 7
3.3 Disturbance due to CHISEL 8
3.3.1 Second Bit Effect 8
3.3.2 Disturbance in Neighboring Cell 12
Chapter 4 Monte Carlo Analysis of Program Disturb 16
4.1 Introduction 16
4.2 Procedure of Monte Carlo Device Simulation 16
4.3 Results and Discussions 23
4.3.1 Analysis of Impact Ionization 23
4.3.2 Energy and Space Distributions of Injected Charges 23
4.3.3 Relative Charge Injection Rate 28
4.3.4 Substrate Bias Effect 28
4.3.5 Scaling Issues 28
Chapter 5 Conslusions 37
References 38

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