臺灣博碩士論文加值系統

本論文利用多模式資料保存電源阻斷技術與超級阻斷電源阻斷技術的低功率技術，提出了一個新穎的高速低功率抗雜訊的三元內容可定址記憶體。利用這兩項低功率技術，記憶體陣列之漏電流將慘遭大幅削減。在搜尋模式下同時應用超級阻斷電源阻斷技術可同時明顯地降低搜尋功率。利用柏克萊預測模型，在65nm下，一個高速低功率256行×144位元之三態內容可定址式記憶體亦被提出，它可以達到超過50%的漏電流削減，以及9%的搜尋功率削減，並達到0.047 fJ/bit/search的能源表現以及0.23ns之搜尋時間。利用TSMC 0.13μm CMOS 技術來實現電路設計與佈局，顯示出所提出的架構對原本的記憶體陣列增加了19%的面積。

A new high speed, low-power and noise-tolerant ternary content-addressable memories (TCAMs) using multi-mode data retention power gating technique and super cut-off power-gating technique are proposed in this thesis. These two techniques significantly reduce cell leakage current by taking the advantage of input don’t care patterns of IPv6 addressing lookup application. Furthermore, search power is also reduced by applying super cut-off power gating technique under search operation. butterfly match-line scheme reduces switching activity also. A 256-word x 144-bit low-power ternary CAM is also proposed. Based on 65nm Berkeley Predictive Technology Model, simulation results shows that 0.23ns search time and 0.047fJ/bit/search energy metric is achieved. Layout is implemented in TSMC 0.13μm CMOS technology, which indicates a 19% area overhead.

Chapter 1 Introduction 1
1.1 Background 1
1.2 Motivation 2
1.3 Organization 3
Chapter 2 An Overview of Content Addressable Memory 5
2.1 Conventional CAM Architecture 5
2.2 Conventional CAM Cell 6
2.2.1 Binary CAM Cell 6
2.2.2 Ternary CAM Cells 8
2.3 Match-line Structure 11
2.3.1 NOR-type Match-line 12
2.3.2 AND-type Match-line 12
2.4 Applications of CAM 13
2.4.1 Cache Memory 14
2.4.2 Translation Look-aside Buffer 15
2.4.3 Packet Forwarding Using CAM 16
2.4.4 ATM Switches 18
2.5 Low power Content-addressable Memory Designs 19
2.5.1 Method of reducing Match-line power consumption 19
2.5.1.1 Low-Swing Scheme 19
2.5.1.2 Current-Race Scheme 20
2.5.1.3 Selective-Precharge Scheme 21
2.5.1.4 Pipelining Scheme 22
2.5.1.5 Current-Saving Scheme 23
2.5.2 Method of reducing Search-line power consumption 24
2.5.2.1 Hierarchical Search-line Scheme 24
2.5.2.2 Charge-Recycling Search-line Driver 26
2.5.3 Power-Saving CAM architecture 27
2.5.4 Tree Style AND-type Match Lines 30
2.6 Method of Reducing Standby Power 33
2.6.1 Novel Storage Cells for TCAM 33
Chapter 3 Multi-Mode Power Gating Technique 36
3.1 Standby Power 36
3.2 Stacking Effect 40
3.2.1 Self-Reverse Biasing 40
3.2.2 Trade-off Between Delay and Leakage 41

3.3 Power Gating Structures with Concurrent Data Retention and Intermediate mode 42
3.4 Proposed Power Gating Structure 46
3.4.1 Multi-mode Data Retention Power Gating Technique 46
3.4.2 Noise Margin Analysis 47
3.4.3 Simulation Result and Comparisons 48
3.5 Summary 49
Chapter 4 Low Power Schemes for Energy-Efficient TCAM Design 51
4.1 IPv6 Addressing Architecture 52
4.1.1 Unspecified Unicast Addresses 53
4.1.2 Loopback Unicast Addresses 53
4.1.3 Global Unicast Addresses 53
4.1.4 Local-Use IPv6 Unicast Addresses 54
4.2 IP Address Lookup 54
4.3 IPv6 Prefix Length Distribution in The Router 57
4.4 Energy Efficient Ternary Content Addressable Memory 58
4.4.1 Butterfly Match-Line Scheme 59
4.4.2 XOR-Based Conditional Keeper 60
4.4.3 Don’t Care Based Power Gating Match-line Scheme 62
4.4.4 Don’t Care Based Hierarchy Search-Line Scheme 63
4.5 Architecture 64
4.5.1 Match-line Scheme 66
4.5.1.1 Butterfly AND-type Match-line Scheme for IPv6 66
4.5.1.2 Applying Don’t-care Based Power-Gating Technique 67
4.5.2 Ternary CAM Cell 68
4.5.3 Don’t-care Based Hierarchical Search-line Scheme for IPv6 70
Chapter 5 Super Cut-off Power Gating TCAM Design with Leakage Current Reduction 71
5.1 Power Sources in Digital CMOS Circuits 72
5.1.1 Dynamic Power 72
5.1.2 Short-Circuit Power 72
5.1.3 Leakage Power 72
5.1.4 Low-Power CAM Design 73
5.2 MOSFET Structure Capacitances 73
5.2.1 Gate Capacitances 73
5.2.1.1 Overlap Capacitances 74
5.2.1.2 Gate-to-Channel Capacitances 75
5.2.2 Junction Capacitances 76
5.2.2.1 Bottom-Plate Junction Capacitances 76
5.2.2.2 Side-Wall Junction Capacitances 77
5.3 Super Cut-off Power Gating TCAM Structure 77
5.3.1 Introduction to Super Cut-off Technique 78
5.3.1.1 Concept of Super Cut-off Technique 78
5.3.1.2 Zigzag Super Cut-off Technique 79
5.3.2 Proposed Super Cut-off Power Gating Technique 82
5.3.2.1 Architecture 82
5.3.2.2 Implementation of Control Circuits and Voltage Generator 83
5.3.3 Simulation Result and Analysis 84
5.4 Proposed Low Power Ternary Content-Addressable Memory 87
5.4.1 Multi-mode Data Retention Power Gating Technique 87
5.4.2 Super Cut-off Power Gating Technique 89
5.4.3 The Overall Architecture 90
5.5 Simulation Result and Comparisons 90
5.6 Layout and the Post-Simulation 93
5.7 Summary 95
Chapter 6 Conclusions 97
6.1 Conclusions 97
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