臺灣博碩士論文加值系統

隨著製程之進步，晶片上的核心數目與核心間的資料傳輸量急遽增加。傳統使用共享匯流排做為核心間的連接方式功效不彰。應用網路連接核心的單晶片網路因能大幅提升傳輸效率，是近年新興又熱門的研究領域。單晶片網路的效能可由功率、速度、面積這三方面來評估。功率及速度由網路拓樸及其所使用的路由器數目決定；面積則是與佈局有關。不同於以往，本論文提出新的單晶片網路設計流程－先完成與效能密切相關的拓樸設計而後再做佈局規劃，並且突破前人使用複雜而耗時的演算法的缺點。實驗結果證實，本論文中所產生的網路拓樸保證符合路由器數目的限制，並且保證決不會造成資料傳輸的交互等待因而引發系統停滯。更甚者，在使用與前人一樣甚至更少的路由器數目，並保有前兩項特點之下，仍能達成低功耗的目地。

Abstract (Chinese) i
Abstract ii
Acknowledgements iii
List of Tables vi
List of Figures vii
Chapter 1. Introduction 1
1.1 Background . . . . . . . . . . . . . . . . . . . 1
1.2 Previous Works . . . . . . . . . . . . . . . . . 4
1.3 Our Contribution . . . . . . . . . . . . . . . . 5
1.4 Organization . . . . . . . . . . . . . . . . . . 6
Chapter 2. Preliminaries and Problem Definition 8
2.1 Communication Trace Graph . . . . . . . . . . . .8
2.2 Main Components in NoC . . . . . . . . . . . . . 8
2.3 Router Architecture . . . . . . . . . . . . . . 10
2.4 Physical Link Model . . . . . . . . . . . . . . 10
2.5 Power Model . . . . . . . . . . . . . . . . . . 10
2.6 Timing Model . . . . . . . . . . . . . . . . . .11
2.7 Problem Definition . . . . . . . . . . . . . . .12
Chapter 3. New Methodology 14
3.1 Phase I—Topology Generation . . . . . . . . . .14
3.1.1 Problem Formulation of Topology Generation . .14
3.1.2 The TG Algorithm . . . . . . . . . . . . . . .15
3.2 Phase II—Floorplanning . . . . . . . . . . . . 17
3.2.1 Problem Formulation of Floorplanning . . . . .18
3.2.2 The FP Algorithm . . . . . . . . . . . . . . .19
Chapter 4. Experimental Results 23
4.1 Benchmark Applications . . . . . . . . . . . . .23
4.2 Experimental Setup . . . . . . . . . . . . . . .23
4.3 Discussion . . . . . . . . . . . . . . . . . . .25
Chapter 5. Conclusions 30
Bibliography 31

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