臺灣博碩士論文加值系統

具有高操作頻率且高傳輸速率的通訊系統已被視為次世代通訊系統的主軸。在近幾年，60-GHz附近的頻帶中，已有7-GHz的頻寬被釋出做為高速短距離通訊系統使用。此頻帶具有可應用在高達十億位元高傳輸速率的無線個人網路(WPAN)以及點對點傳輸上的潛力。
此論文中介紹了一個與三倍頻器整合的60-GHz CMOS直接降頻式接收器。此接收器包含了低雜訊放大器、降頻混頻器以及三倍頻器等電路，並且使用了0.13-um CMOS技術來設計並製造。藉由使用三倍頻器，所需要的頻率合成器之操作頻率可以由60 GHz降至20 GHz，並使得頻率合成器的實現變得較為容易。根據量測結果顯示，此電路由於佈局時發生的錯誤，使得增益降至13.9 dB。量測結果證實此電路具有50.5 GHz 到58.5 GHz的頻寬，以及在中心頻率54.5 GHz具有-12 dBm的輸入1-dB增益壓縮點與-5 dB的S11特性。並且，從修改後的模擬結果可知，雜訊大小約在9.2 dB左右。此電路操作在1.2 V的供應電壓下，並且消耗11.4 mW的直流功率。除此之外，此論文中也討論了造成頻率漂移以及增益降低的原因。從討論可知，若小心佈局電路，此架構的接收器可達到比量測結果更優異的特性，並且非常適合用在低功率，高傳輸速率的無線通訊系統中。
除了60-GHz接收器之外，此論文也提出一個70-GHz的低雜訊放大器電路。在此低雜訊放大器中，我們使用了三級串接的共源級架構來取代高頻常見的疊接架構以提升雜訊特性。並且可將電路的供應電壓降至0.8 V來達到低電壓以及低功率的設計。量測結果顯示此低雜訊放大器在中心頻率具有10.9 dB增益，以及小於-12 dB的S11以及S22特性。由模擬結果可知在67.8 GHz的雜訊大小可達到5.1 dB。 除此之外，此電路涵蓋了65至72 GHz的頻寬，非常適合用在寬頻的應用上。最後，這個操作在0.8-V低電壓的電路所消耗的功率只有5.4 mW，並被實現在0.38　mm2的晶片面積中。此結果證實了此電路非常適合用在50 GHz以上高頻的接收器中。

In the next-generation wireless communication, high data rate transmission with a high operating frequency is expected. Over the past few years, the 7-GHz unlicensed band around 60 GHz has been released for high-speed and short-range communication systems. It has great potential in application of high data-rate wireless personal–area network (WPAN), high speed WLAN and point-to-point link, with possible data rate of gigabits per second.
In this thesis, a 60-GHz CMOS direct-conversion receiver integrated with a frequency tripler is presented. The proposed receiver which consists of a low-noise amplifier (LNA), a down-conversion mixer, output buffers, and a frequency tripler are designed using 0.13-um CMOS technology. By using a frequency tripler, the operating frequency of the frequency synthesizer can be reduced from 60 GHz to 20 GHz. This makes the implementation of the frequency synthesize much easier. Based on measurement results, as a result of the layout error, the receiver power gain is decreased to 13.9 dB. The measurement result presents the main circuit characteristics: covering 3dB-bandwidth from 50.5 GHz to 58.5 GHz, input-referred 1-dB compression point of -12 dBm, input return loss of -5 dB at center frequency of 54.5 GHz and consumes 11.4 mW from 1.2-V power supply. Moreover, the re-simulated noise figure (NF) considering the undesired effects is about 9.2 dB. Afterwards, the reasons of malfunction which cause the frequency shift and gain reduction are discussed here. From the discussion, with the carefully layout, the proposed receiver can achieve much better performance than measurement and is confirmed to be suitable for low-power and high data-rate wireless communication systems.
Besides the 60-GHz receiver, a 70-GHz LNA is also presented. In the proposed LNA, three-stage common-source topology is used instead of cascode configuration to improve the noise performance. As a direct consequence of the use of common source structure in the proposed LNA, the voltage can be reduced to 0.8 V, which is much lower than that for the cascode structure. Therefore, the level of power consumption can be reduced greatly. The measured LNA gain is about 10.9 dB and the input and output return losses are lower than -12 dB at center frequency with the simulated noise figure of 5.1 dB. Furthermore, the 3-dB bandwidth covers from 65 GHz to 72 GHz which is suitable for wideband applications. Finally, this circuit can be operated on a low supply voltage of 0.8-V and only consumes 5.4 mW with a 0.38 mm2 chip area. It is proved that the proposed LNA is feasible to use it in building fully integrated receiver at frequency of above 50 GHz.

Chinese Abstract………………………………………………… i
English Abstract………………………………………………… ii Contents………..…………………………………………………iii
Table Captions………………………………………………… viii
Figure Captions……………………………………………………ix

Chapter 1 Introduction 1
1.1 Background 1
1.2 Reviews on CMOS RF Front-end Receivers 3
1.2.1 Receiver Architectures 4
1.2.2 Review on 60-GHz CMOS Receivers 7
1.2.3 Review on Building Blocks of CMOS Receiver 10
1.2.4 Review on Frequency Multiplier 13
1.3 Motivation 15
1.4 Thesis Organization 15
Chapter 2 A High-Frequency Frequency Multiplier 16
2.1 Design of the Frequency Tripler 16
2.1.1 Operational Principle 16
2.1.2 Design Considerations 18
2.1.3 Circuit Realization 19
2.1.4 Simulation Results of Frequency Tripler 23
2.2 Comparison with Previous Works 27
Chapter 3 RF Front-End Circuits 29
3.1 Receiver Architecture and Design Considerations 29
3.2 Low Noise Amplifier Design 34
3.2.1 Design Consideration 35
3.2.2 A 0.8-V 70-GHz Three-stage Cascaded Common-source Topology with Inductive Feedback 39
3.2.3 A 60-GHz Two-stage Low Noise Amplifier 42
3.2.4 Simulation Results of LNAs 46
3.3 Down Conversion Mixer 54
3.3.1 Design Consideration of Mixer 55
3.3.2 Circuit Realization of Mixer 59
3.3.3 Simulation Results of Mixer 63
3.4 Simulation Results of Receiver Front-end 65
Chapter 4 Experiment Results 71
4.1 Layout Description 71
4.2 Measurement Consideration and Setup 74
4.3.1 Measurement of 70-GHz Low Noise Amplifier 74
4.3.2 Measurement of 60-GHz Receiver 78
4.3 Experiment Results 81
4.3.1 Experiment Results of 70-GHz LNA 81
4.3.2 Experiment Results of 60-GHz Receiver 86
4.4 Discussions and Comparisons 89
Chapter 5 Conclusions and Future Work 95
5.1 Conclusions 95
5.2 Future work 96
Appendix 100

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