臺灣博碩士論文加值系統

本論文提出一個可用在每秒一百億位元傳輸的序列輸出入端的新型樹狀序列器，利用九十度相位差異的時脈來作為類似開關控制，以排除一般設計中對於時序再重置方法的需要，因此在功率消耗與電路面積上能有顯著降低。模擬結果顯示在每秒一百億位元傳輸，相較於一般的序列器，所推薦的序列器消耗百分之七十的功率以及百分之二十二的面積。
在本篇論文中，我們設計了一個每秒一百億位元傳輸器。使用台積電 0.13 m 2P8M CMOS 製程來實現，此傳輸電路在1.2伏特的電源供應下消耗功率27毫瓦。
另外，我們也提出在晶片內部傳輸的通道模型以及所對應一公分通道長的低功率驅動器設計。

List of Contents V
List of Tables VI
List of Figures VII
Chapter 1 Introduction 1
1.1 CMOS HIGH-SPEED SERIAL LINKS 1
1.2 MOTIVATION 3
1.3 THESIS ORGANIZATION 4
Chapter 2 Background Study 5
2.1 OTHER STRUCTURE OF SERIALIZER 5
2.2 SHIFT-REGISTER TYPE SERIALIZER 8
2.3 SINGLE-STAGE TYPE SERIALIZER 9
2.4 CONVENTIONAL TREE-TYPE SERIALIZER 10
Chapter 3 The Novel Tree-Type Serializer 12
3.1 FUNCTIONAL BLOCKS 12
3.2 COMPARISON OF THREE STRUCTURES 15
3.2.1 ANALYSIS OF NOVEL TREE-TYPE AND SINGLE-STAGE SERIALIZER 16
3.2.2 COMPARE THREE ARCHITECTURES BY HSPICE SIMULATION 20
3.2.2.1 SINGLE-STAGE SERIALIZER 21
3.2.2.2 NOVEL TREE-TYPE SERIALIZER 24
3.2.2.3 CONVENTIONAL TREE-TYPE SERIALIZER 27
3.2.3 THE COMPARISON RESULTS AS FIGURES AND TABLES 31
3.3 SUMMARY 37
Chapter 4 Transmitter Circuit Design 38
4.1 INTRODUCTION 38
4.2 CIRCUIT DESIGN 38
4.2.1 MUX 8-TO-1 39
4.2.2 MUX 4-TO-1 42
4.2.3 MUX 32-TO-1 44
4.2.4 DRIVER 45
4.3 SIMULATION RESULT 45
4.4 IMPLEMENTATIONS 48
4.5 SUMMARY 52
Chapter 5 Measurement 53
5.1 OFF CHIP 53
5.2 ON WAFER 56
Chapter 6 On-Chip channel model analysis and low power driver 59
6.1 On-Chip Channel Model Analysis 59
6.2 Low Power Driver 62
Chapter 7 Conclusion 65
7.1 CONCLUSION 65
Bibliography 67

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