臺灣博碩士論文加值系統

本論文提出了一個利用控制弦波對齊演算法實現應用於三角積分調變器的內建自我測試電路。為了得到噪聲畸變比 (SNDR) 的值，傳統上所使用的方法為在頻域上作分析，透過快速富利葉轉換法推導而得；本論文所採用的方式則是參考控制弦波對齊演算法的測試流程，分別在時域上作運算以得到訊號功率以及雜訊與諧波失真總功率。經由重新修改了控制弦波對齊演算法的流程後，所提出的內建自我測試架構可免於使用數位運算處理器、記憶體、或是並列式乘法器等會佔據大量晶片面積的電路。為了驗證其可行性，我們使用了一個加入數位可測試設計的二階類比Σ-Δ調變器作為待測電路。經由量測結果得知，經由所提出之輸出響應分析器的分析結果與傳統 FFT 分析法做比較，兩者差異值擁有 0.86 dB 的平均值和 1.07 dB 的標準差。所提出之測試架構同時擁有低成本效益、高測試速度以及高量測精準度等優點，適用於內建式自我測試應用中。

An implementation of a BIST circuitry for sigma-delta modulators based on control sine wave fitting method is presented. Instead of using Fast Fourier Transform (FFT) to derive the signal-to-noise-and-distortion ratio (SNDR) in frequency domain, the pro-posed architecture uses the modified control sine wave fitting procedure to separately calculate the signal power and the total harmonic distortion noise power in time domain. It requires neither parallel multiplier nor complex CPU/DSP and bulky memory thus achieving a low cost. To verify its functionality, a second order de-sign-for-digital-testability Σ-Δ modulator is used as the modulator under test (MUT). Measurement results show that the SNDR difference between conventional FFT results and the corresponding ones of the proposed BIST scheme have a mean and a standard deviation of 0.86 dB and 1.07 dB respectively. The proposed BIST scheme has the ad-vantages of compact hardware, a short test time, and high testing accuracy that make it suitable for embedded BIST applications.

中文摘要................................................iii
Abstract.................................................iv
誌謝......................................................v
目錄.....................................................vi
圖目錄...................................................ix
Chapter 1 緒論............................................1
1.1. 研究動機與目的.....................................1
1.2. 測試類比電路所遭遇之難題與解決方案.................2
1.3. 待測Σ-Δ類比數位轉換器..............................3
1.4. BIST規格與目標.....................................4
1.5. 論文章節與組織.....................................5
Chapter 2 檢視目前領導潮流之研究..........................6
2.1. 基於直方圖演算法之內建自我測試技術.................6
2.1.1. 基本觀念闡述...................................6
2.1.2. 硬體實現之分析與考量...........................7
2.1.3. 提高可行性之相關研究...........................8
2.1.4. 評估與討論....................................13
2.2. 基於頻譜分析法(快速富利葉轉換)之內建自我測試技術..13
2.2.1. 基本觀念闡述..................................13
2.2.2. 硬體實現難處之分析與考量......................15
2.3. 基於時域分析法之內建自我測試技術..................16
2.3.1. 基本觀念闡述..................................16
2.3.2. 控制弦波對齊演算法............................18
2.3.3. 評估與討論....................................23
Chapter 3 系統架構.......................................25
3.1. 系統架構簡述......................................25
3.2. 數位可測試性設計之二階Σ-Δ類比數位轉換器...........27
3.3. 位元串流產生器....................................30
3.3.1. 基本觀念......................................30
3.3.2. 一個具有良好成本效益的數位振盪器..............37
3.4. 相位誤差補償器的設計..............................42
Chapter 4 系統之操作流程與硬體實現.......................49
4.1. 操作流程..........................................49
4.1.1. 週期一：計算偏移誤差..........................51
4.1.2. 週期二：計算增益誤差..........................52
4.1.3. 週期三：計算雜訊與弦波失真功率................53
4.2. 硬體實現..........................................55
4.2.1. 位元串流產生器之硬體實現......................55
4.2.2. 輸出響應分析器之硬體實現......................56
Chapter 5 模擬結果.......................................58
5.1. 模擬狀況之設定....................................58
5.2. 模擬結果與討論....................................59
5.3. 以Verilog實現系統架構.............................64
5.3.1. 控制邏輯電路的實現............................64
5.3.2. 數位晶片實現流程之相關報告....................67
Chapter 6 量測結果.......................................72
6.1. 量測環境之設定....................................72
6.2. 量測結果與討論....................................72
Chapter 7 結論與未來發展.................................77
Reference................................................79
自傳.....................................................82

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