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研究生:陳昱企
論文名稱:選擇性磊晶成長在升高式源/汲極應用之研究
論文名稱(外文):A Study of Selective Epitaxial Growth (SEG) for Raised Source/Drain (RSD) Application
指導教授:吳耀銓
學位類別:碩士
校院名稱:國立交通大學
系所名稱:工學院碩士在職專班半導體材料與製程設備組
學門:工程學門
學類:材料工程學類
論文種類:學術論文
論文出版年:2006
畢業學年度:95
語文別:中文
論文頁數:93
中文關鍵詞:選擇性磊晶升高式源/汲極短通道半導體
外文關鍵詞:Selective Epitaxial GrowthRaised Source DrainShort ChannelSemiconductor
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金屬氧化物半導體元件的製造技術必須不斷的突破,才能解決元件尺寸縮小所面臨越來越嚴重的短通道效應。選擇性磊晶成長製程,應用於升高式的源/汲極,可以有效地改善短通道效應。本論文研究的目標,就是在研究選擇性的磊晶製程,與升高式源/汲極的元件特性。先以TCAD 模擬一般元件與升高式源/汲極元件,N型與P型雜質摻雜的分佈,Vt Roll-off 以及DIBL等短通道效應的比較,再以兩種選擇性磊晶製程做出升高式源/汲極元件,以SIMS、TEM來觀察磊晶製程結果,並且量測元件來比較元件電性。驗證了選擇性磊晶製程應用於升高式的源/汲極元件的可行性,並且使短通道效應得到大幅改善。相信此技術對於半導體元件的持續微縮會有重大的貢獻。
As the metal-oxide-semiconductor device dimension shrinking, engineers need to develop breakthrough technologies to fix the more and more serious short channel effects. The selective epitaxial growth applied on the raised source/drain is an effective method to alleviate the short channel effects. This study mainly focuses on the process of the selective eptaxial growth and the device characteristics of the raised source/drain. First, we simulated the N and P doping profiles, Vt Roll-off and DIBL conditions on raised source/drain and traditional devices. Then, we processed selective epitaxial growth to form raised source/drain devices by two approaches. In the experiment results analysis, SEM, TEM and SIMS were adopted for the physical performance of the process. And, the device characteristcs were tested by electrical probes to compare the electrical performance. This study has proved that the selective eptaxial growth for raised source/drain is a feasible method and it improves the device performance in the short channel behaviors. This technology will play an important role in the nano device era.
中文提要 ………………………………………………………… i
英文提要 ………………………………………………………… ii
誌謝 ………………………………………………………… iii
目錄 ………………………………………………………… iv
表目錄 ………………………………………………………… vi
圖目錄 ………………………………………………………… vii
一、 緒論…………………………………………………… 1
二、 短通道效應…………………………………………… 6
2.1 什麼是短通道效應…………………………………… 6
2.1.1 臨界電壓下降 (Vt Roll-Off)……………………… 6
2.1.2 汲極引發的位能下降 (DIBL).……………………… 9
2.1.3 擊穿效應 (Punch Through)………………………… 10
三、 選擇性磊晶成長技術介紹………………………… 11
3.1 矽磊晶成長…………………………………………… 11
3.2 什麼是選擇性磊晶成長技術………………………… 13
3.3 選擇性磊晶成長技術重要參數……………………… 14
3.3.1 製程溫度 (Process Temperature)…………………. 15
3.3.2 表面潔淨度 (Surface Cleaness)…………………… 15
3.3.3 選擇性 (Selectivity)…………………………………16
3.3.4 面向與凸塊 (Facet and Bump)……………………… 16
3.3.5 負載效應 (Loading Effect)………………………… 19
四、 升高式源/汲極………………………………………… 20
4.1 結構….………………………………………………… 20
4.2 升高式源/汲極的模擬………………………………… 20
4.2.1 DRAM array cell gate………………………………21
4.2.2 NMOS…………………………………………………… 22
4.2.3 PMOS…………………………………………………… 23
4.3 元件特性模擬………………………………………… 25
五、 實驗介紹及整合製程敘述…….……………………… 28
5.1 實驗目標………….…………………………………… 28
5.2 選擇性磊晶製程…….………………………………… 28
5.2.1 製程A…………………………………………………… 29
5.2.2 製程B…………………………………………………… 29
5.3 整合製程……………………………………………… 30
5.3.1 STI……………………………………………………… 31
5.3.2 Well Implant………………………………………… 32
5.3.3 Gate…………………………………………………… 33
5.3.4 SEG……………………………………………………… 35
5.3.5 S/D Implant…………………………………………… 35
5.3.6 Contact Implant………………………………………36
5.3.7 Contact via and line……………………………… 37
5.4 量測與分析…………………………………………… 40
5.4.1 測試元件介紹………………………………………… 40
5.4.2 測試設備……………………………………………… 43
六、 結果與討論…….……………………………………… 44
6.1 磊晶製程物理性質分析.……………………………… 44
6.1.1 製程A…………………………………………………… 44
6.1.2 製程B…………………………………………………… 47
6.2 選擇性磊晶製程分析…..…………………………… 50
6.2.1 製程A…………………………………………………… 50
6.2.2 製程B…………………………………………………… 63
6.3 元件電性分析………………………………………… 71
6.3.1 Vt Roll-Off……………………………………………72
6.3.2 DIBL………………………………………………………72
6.3.3 Ids………………………………………………………74
6.3.4 Junction Leakage………………………………………76
6.3.5 Gate to S/D overlap capacitance…………………77
6.3.6 S/D Sheet Resistance………………………………78
6.3.7 Contact Resistance……………………………………79
七、 結論…….…………………………………………… 83
參考文獻 ………………………………………………………… 84
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