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研究生:劉晉煒
研究生(外文):Chin-Wei Liu
論文名稱:高穩定度積體式非晶矽薄膜電晶體之閘極驅動電路
論文名稱(外文):Highly Reliable Integrated Amorphous Silicon Thin Film Transistor Gate Driver
指導教授:戴亞翔
指導教授(外文):Ya-Hsiang Tai
學位類別:碩士
校院名稱:國立交通大學
系所名稱:顯示科技研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:英文
論文頁數:46
中文關鍵詞:非晶矽薄膜電晶體可靠度液晶顯示器閘極驅動電路水平掃描電路
外文關鍵詞:a-Si TFTreliabilityLCDgate driverscan driver
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非晶矽薄膜電晶體(a-Si TFTs)為大面積面板電路之主流元件,由於其製程上低溫低成本以及在電性與空間上的均勻分佈等優點,在平面顯示器,或者影像陣列等大面積面板電路當中,皆以非晶矽薄膜電晶體作為畫素電路。近年來,為了實現將系統整合於面板之上(System-on-Panel),積體式非晶矽薄膜電晶體閘極驅動電路在液晶顯示器(Liquid Crystal Display, LCD)上的應用備受關注,不僅符合低成本製程,同時也能節省LCD水平掃描線驅動IC 的成本。在本論文中,提出了一個高穩定度的非晶矽薄膜電晶體之移位暫存器,適用於主動陣列液晶顯示器(Active Matrix LCD)的水平掃描驅動電路,且根據使用於電路中的非晶矽薄膜電晶體元件可靠度的量測,預估此電路的操作壽命將超過15000小時。
The amorphous silicon thin-film transistors (a-Si TFTs) technology is the mainstay of large area electronics such as flat panel displays, and imaging arrays due to its spatial uniformity and low-temperature processing cost benefits. Recently, integrated driver circuit using a-Si:H TFTs on glass is gaining attention in liquid crystal display LCD technology, since it can reduce fabrication cost by eliminating driver ICs and related processes. In this thesis, a reliable shift register consisted of amorphous silicon thin film transistors is proposed for scan driver circuit of active matrix liquid crystal display (AMLCD). The lifetime of proposed circuit is evaluated based on the reliability measurement data of the a-Si TFTs used and it is estimated to over 15000 hours. Therefore, a highly reliable scanning circuit can be achieved.
Chinese Abstract ……………………………………………I
English Abstract ……………………………………………II
Acknowledgements ……………………………………………III
Contents ………………………………………………………IV
Table Captions ………………………………………………VI
Figure Captions………………………………………………VII

Chapter 1 Introduction
1.1 Development of Display ……………………………… 1
1.2 Amorphous silicon TFTs……………………………… 1
1.3 Integrated a-Si gate driver (ASGD)……………………2
1.4 Instability of a-Si TFT……………………………… 3
1.5 Thesis organization ………………………………… 4

Chapter 2 Configuration of ASGD
2.1 Typical configuration ……………………………… 5
2.2 Proposed configuration ……………………………… 6
2.3 Function of buffer ............................ 6


Chapter 3 Proposed Circuit
3.1 Low Pull-Down Voltage (LPDV) ASGD………………………… 8
3.2 Advanced Low Pull-Down Voltage (ALPDV) ASGD ………… 9
3.3 Robust Low Pull-Down Voltage (RLPDV) ASGD ……………10
3.4 The critical TFTs in circuit RLPDV ASGD……………… 12
3.4.1 The lifetime of critical TFTs with DC stress … 12
3.4.2 The lifetime of the critical TFT with AC stress …13

Chapter 4 Conclusion ……………………………………… 15

References ……………………………………………………… 43
Reference
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