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研究生:黃政德
研究生(外文):Zheng-De Huang
論文名稱:應用於超寬頻系統之功率放大器與低雜訊放大器之晶片設計
論文名稱(外文):Chip Design of Power Amplifier and Low Noise Amplifier for Ultra-Wideband Applications
指導教授:林志明林志明引用關係
指導教授(外文):Zhi-Ming Lin
學位類別:碩士
校院名稱:國立彰化師範大學
系所名稱:積體電路設計研究所
學門:商業及管理學門
學類:其他商業及管理學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:中文
論文頁數:48
中文關鍵詞:超寬頻系統功率放大器低雜訊放大器
外文關鍵詞:Ultra Widebandpower amplifierlow noise amplifier
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本論文主要是利用台積電的0.18微米1P6M CMOS製程設計應用於超寬頻系統前端電路中之功率放大器與低雜訊放大器。第一顆晶片是用於傳送端超寬頻系統之功率放大器設計與分析,我們利用共閘級放大器來達到輸入端的阻抗匹配,再利用疊接放大器與柴比雪夫帶通濾波器來達到較高的輸出功率與阻抗匹配。模擬結果顯示此一放大器在3.1GHz到10.6GHz 頻率下有11.5dB的最高功率增益(S21),輸入反射係數(S11)與輸出反射係數(S22)小於-10dB,輸出功率在1dB壓縮點達到4.7dBm,總消耗功率為23.4mW。
第二顆晶片中,我們利用電流重複使用技術為基本架構來設計一個超寬頻系統之低雜訊放大器,許多文獻採用柴比雪夫帶通濾波器來當作輸入端的阻抗匹配,在本電路設計中為了達到較低的雜訊指數,我們採用一個簡單的低通濾波器來當作輸入匹配網路,不僅得到較低的雜訊指數並且對於面積也有節省。模擬結果顯示此放大器在3.1GHz到10.6GHz 頻率下得到最高16.1dB的增益及1dB的變化量,S11與S22小於-10dB,最低雜訊指數為2.3dB,輸入功率的1dB壓縮點(P1dB)為-21dBm與-9dBm的輸入三階截斷點(IIP3),總消耗功率為17.7mW。
摘要 i
ABSTRACT ii
謝誌 iii
TABLE OF CONTENTS iv
LIST OF FIGURES vi
LIST OF TABLES viii

CHAPTER 1 INTRODUCTION 1
1.1 Ultra-Wideband Communication System 1
1.2 Motivation 2
1.3 Organization of the Thesis 2

CHAPTER 2 FUNDERMANTAL OF RF AMPLIFIER DESIGN 4
2.1 Introduction 4
2.2 Scattering Parameters 4
2.3 Power Gain 5
2.3.1 Transducer power gain 6
2.3.2 Available power gain 6
2.3.3 Operation power gain 6
2.4 Stability 7
2.5 Noise Figure 8
2.6 Linearity 11
2.6.1 Harmonic distortion 11
2.6.2 Intermodulation distortion (IMD) 12
2.6.3 Gain compression (P1dB) 13
2.6.4 Third order intercept point (IIP3 and OIP3) 13

CHAPTER 3 UWB POWER AMPLIFIER 16
3.1 Topologies of Input Stage 16
3.1.1 Common gate amplifier 19
3.1.2 Input stage 21
3.2 Output Stage 21
3.3 UWB Power Amplifier 23
3.4 Layout 24
3.5 Simulation Results 25
3.6 Testing Setup 30
3.7 Measurement Results and Conclusion 30

CHAPTER 4 UWB LOW NOISE AMPLIFIER 33
4.1 A Reported Ultra-Wideband Low Noise Amplifier 33
4.2 Circuit Topology and Design Concepts 35
4.2.1 Current-reused technique 35
4.2.2 Wideband matching 35
4.2.3 Minimum noise figure 36
4.3 Layout 38
4.4 Simulation Results 39

CHAPTER 5 CONCLUSIONS 45
REFERENCES 46
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[2] WPAN High Rate Alternative PHY Task Group 3a (TG3a), IEEE 802.15, 2007 [Online]. Available: http://www.ieee802.org/15/pub/ TG3a.html
[3] Kai Chang, Inder Bahl, and Vijay Nair, RF and Microwave Circuit and Component Design for Wireless systems, John Wiley & Sins, 2002.
[4] Guillermo Gonzalesz, Microwave Transistor Amplifier Analysis and Design, Prentice-Hall, Inc. Upper Saddle River, 1997.
[5] Behzad Razavi, RF Microelectronics, Upper Saddle River, NJ: Prentice Hall, 1998.
[6] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, 1st ed. New York: Cambridge Univ. Press, 1998.
[7] S. Jose, H. J. Lee, and D. Ha, “A low-power CMOS power amplifier for ultra wideband (UWB) applications,” IEEE circuit and systems Symposium, vol. 5, pp. 5111–5114, 2005.
[8] C. Lu, A. V. Pham, and M. Shaw, “A CMOS power amplifier for full-band UWB transmitters,” IEEE Radio Frequency Integrated Circuits Symposium, June 2006.
[9] H. C. Hsu, Z. W. Wang , and G. K. Ma, “A low power CMOS full-band UWB power amplifier using wideband RLC matching method,” Electron Devices and Solid-State Circuits, pp. 233–236, Dec. 2005.
[10] V. Sumit, S. Jung, and Y. Joo, “Ultra wideband CMOS low noise amplifier with active input matching,” Ultra Wideband systems Joint Conference, pp. 415–419, 2004.
[11] A. Bevilacqua and A. M. Niknejad, “An ultra-wideband CMOS LNA for 3.1 to 10.6 GHz wireless receiver,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2259–2268, Dec. 2004.
[12] C. W. Kim, M. S. Kang, P. T. Anh, H. T. Kim, and S. G. Lee; “An ultra-wideband CMOS low noise amplifier for 3 to 5-GHz UWB system,” IEEE Journal of Solid-State Circuits, vol. 40, no. 2, pp. 544–547, Feb. 2005.
[13] Y. Lu, K. S. Yeo, A. Cabuk, J. Ma, A. Do, and Z. Lu, “A novel CMOS low noise amplifier design for 3.1 to 10.6 GHz ultra-wide-band wireless receivers,” IEEE Circuit and system, vol. 59, no. 8, pp. 1683–1692, Aug. 2006.
[14] M. T. Reiha, and J.R. Long, “A 1.2 V reactive-feedback 3.1–10.6 GHz low-noise amplifier in 0.13 um CMOS,” IEEE Journal of Solid-State Circuits, vol. 42, no. 5, pp. 1023–1033, May 2007.
[15] Y. J. Lin, S. H. Hsu, J. D. Jin, and C. Y. Chan, “A 3.1–10.6 GHz ultra-wideband CMOS low noise amplifier with current-reused technique,” IEEE Microwave and wireless component letters, vol. 17, No.3, pp. 232–234, March 2007.
[16] H. L. Kao, Albert Chinb, K. C. Chang, and S. P. McAlisterc, “A low-power current-reuse LNA for ultra-wideband wireless receivers from 3.1–10.6 GHz,” Silicon Monolithic Integrated Circuit in RF System, pp. 257–260, Jan. 2007.
[17] A. Ismail and A. A. Abidi, “A 3–10-GHz low-noise amplifier with wideband LC-ladder matching network,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2269–2277, Dec. 2004.
[18] Y. Lu, R. Krithivasan, W. M. L. Kuo, and J. D. Cressler, “A 1.8–3.1 dB noise figure (3–10 GHz) SiGe HBT LNA for UWB applications,” in Proc. IEEE RFIC Symposium, pp. 59–62, June 2006.
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