臺灣博碩士論文加值系統

對於高品質CMOS電路而言，IDDQ測試曾經是有效且高效率之測試方式。然而在即將來臨之奈米製程下，電流解析度逐漸地受限於漏電流的上升與變異。另一方面，為解決靜態功率消耗之問題，在商業考量設計流程下，電源閘控的功耗管理方式已被標準化。本論文乃基於電源閘控之功耗管理方式已存在之需求，發展一個具可調適資料保存性之基本CMOS邏輯閘電路，不僅可減少於功耗管理下使用電源閘控時的尖峰功耗電流與喚醒時間，並能大幅改善電源閘控狀態下進行睡眠模式之電流解析度。
與現存由多門檻電壓技術（MTCMOS）所實現的雙端閘控標準元件做比較，僅增加一點點額外面積用以維持資料保存的功能，藉由選擇一個可調適性電源閘控開關去截止與擺脫規律性之漏電流，透過已將資料保存開啟的電晶體，可以有效低測試到橋接電流。從使用小電路與ISCA89標準電路的實驗結果來看，其電流解析度改善可達大約64倍。

IDDQ testing used to be an effective and efficient technique for testing high quality CMOS circuits. However the current resolution is gradually confined by leakage elevation and variation in the coming nanotechnology. On the other hand, to resolve the issue on static power dissipation, power-gating power management has been standardized in commercial reference design flow. Based on the existing requirement on power-gating power-management, this thesis is to develop an adaptive data-retention CMOS primitive logic gates that can not only reduce the spike current and wakeup time in power-gating power management but also highly improve the current resolution in the proposed power-gating sleep-mode current test.
Compared to existing double-ended power-gating primitive-logic standard cells implemented by MTCMOS for power-management, only a few overhead is added to maintain the data-retention mechanism. Getting rid of regular leakages cut off by the adaptively selected power gates, the bridging current through the turned-on retention transistors can then be efficiently tested. From experimental results using small examples and ISCAS89 benchmark circuits, about 64 times of current-resolution improvement can be achieved.

第一章 緒論 1
1-1 研究背景 1
1-2 研究動機 4
1-3 本論文簡介 6
1-4 本論文的章節編排 7
第二章 測試原理介紹 9
2-1 超大積體電路測試原理 9
2-2 電流測試原理 10
2-3 功耗評估 15
第三章 先前相關之研究與技術 18
3-1 電流測試觀念 18
3-2 Zigzag Super-Cutoff CMOS的結構 19
3-3 提昇電流測試解析度 21
3-4 相關電源閘控低功耗設計方面 24
第四章 本論文提出之IDDS架構 27
4-1 問題陳述與定義（Problem Formulation） 27
4-1-1 通閉路電流模型 27
4-1-2 超閉路開關（Super-cutoff） 28
4-1-3 門檻電流（Ith） 30
4-2 ASCCMOS架構（Adaptive supper cutoff CMOS） 31
4-2-1 睡眠控制訊號閘控迴路（Control-gated configuration） 31
4-2-2 電源開關維持旁路（Keeper-based configuration） 32
4-2-3 設計並對可能之ASCCMOS基本元件電路進行分類與比較 34
4-2-4 定義睡眠模式下之工作模式 35
4-3 叢集架構之配置 35
4-4 睡眠電流測試程序 36
4-5 橋接錯誤的分析 37
4-5-1 錯誤植入電路的探討 39
4-5-2 植入橋接電阻的範圍 40
4-6 分析各種設計之特性比較 41
第五章 實驗結果 43
5-1 BENCH circuit WL面積評估與電流解析度改善度 43
5-2 佈局ASCCMOS基本元件並建立元件庫 44
5-3 以小型電路進行面積、衝擊與元件功能的驗證分析 46
5-3-1 PG架構與ASC架構面積與延遲時間比較 46
5-3-2 LVT架構與ASC架構加入橋接錯誤之可量測範圍 47
5-4 0.13um下線之晶片資料與模擬結果分析 48
第六章 結論 55
參考文獻 56
作者簡歷 59

[1] A. P. Chandrakasan, S. Sheng and R. W. Brodersen,“Low-Power CMOS Digital Design,” IEEE Journal of Solid-State Circuits, vol. 27, no. 4, pp. 473-484, Apr 1992.
[2] T.-C. Huang,“Low-Power Testing for CMOS Logic Circuits,” Ph.D. Dissertation, Nat’l Cheng Kong Univ., Taiwan, Jan 2002.
[3] N. Nicolici and B. M. Al-Hashimi, Power-Constrained Testing of VLSI Circuits. Kluwer, NY. 2003.
[4] International Technology Roadmap for Semiconductors, 2002 Update, Semiconductor Industry Association, [online] http://public.itrs.net.
[5] E. Acar, A. Devgan, R. Rao, Y. Liu, H. Su, S. Nassif and J. Burns,“Leakage and Leakage Sensitivity Computation for Combinational Circuits,” In Proc. Int’l Symp. Low-Power Electronics and Design, pp. 96-99, Aug 2003
[6] W. Liao, J. M. Basile and L. He,“Leakage Power Modeling and Reduction with Data Retention,” In Proc. of International Conference on Computer Aided Design, Nov 2002.
[7] F. Li and L. He, “Maximum Current Estimation Consider-ing Power Gating,” In ACM Proc. Int'l Symp. on Physical Design, pp. 106-111, Apr 2001.
[8] R. Vilangudipitchai and P. T. Balsara,“Power Switch Network Design for MTCMOS, ”In Pro, Int’l Conf. on VLSI Design, pp. 836-839, 2005.
[9] M. Anis, S. Areibi, M. Mahmoud and M. Elmasry, “Dynamic and Leakage Power Reduction in MTCMOS Circuits using an Automated Efficient Gate Clustering Technique,”In Proc. Design Automation Conf., pp. 480-485, June 2002.
[10] K.-S. Min, H. Kawaguchi and T. Sakurai, “Zigzag Super Cutoff CMOS (ZSCCMOS) Block Activation with Self-Adaptive Voltage Level Controller: An Alternative to Clock-Gating Scheme in Leakage Dominant Era,” In IEEE. Int’l Solid-State Circuits Conf. Digest of Technical Papers, pp. 400-401, Feb 2003.
[11] G. Moore, Cramming More Components Onto Integrated Circuits, Electronics, vol. 38, No. 8, April 19, 1965, [online] http://www.intel.com.
[12] M. Garey and D. S. Johnson, “Computers and Intractability: A Guide to theTheory of NP-Completeness,” W. H. Freeman, New York, 1979.
[13] J. P. Roth, “Diagnosis of Automata Failures: A Calculus and a Method,” In Proc. IBM Journal of Research and Development, vol. 10, no.4, pp. 278-291, July 1996.
[14] P. Goel, “An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits,”IEEE Transactions on Computers, vol. C-30, no. 3, pp. 215-222,Mar 1981.
[15] H. Fujiwara and T. Shimono, “On the Acceleration of Test Generation Algorithms,”IEEE Transactions on Computers, vol. C-32, no. 12, pp. 1137-1144, Dec 1983.
[16] A. Keshavarzi, K. Roy and C. Hawkins, “Intrinsic Leakage in Low Power Deep Sub-micron CMOS ICs,” in Proc. International Test Conference, pp. 146-155, Washington, DC, Oct 1997.
[17] T.-C. Huang and K.-J. Lee, “Reduction of Power Consumption in Scan-based Circuits during Test Application by an Input Control Technique. IEEE Trans, ” on CAD of Circuits and Systems, vol. 20, no. 7, pp. 911-917, Jul 2001.
[18] R. Rajsuman, “Iddq Testing for CMOS VLSI,” In Proceedings of the IEEE, pp.544-566, vol. 88, no. 4, April 2000.
[19] K. Raahemifar and M. Ahmadi, “Fault Characterizations and Design-for-Testability Technique for Detecting IDDQ Faults in CMOS/BiCMOS Circuits,” Canadian Conference on Electrical and Computer Engineering, vol. 2, pp.13-16, May 2001.
[20] Tsung-Chu Huang, Ling Li and Yuan-Wei Chao, “IDDS Testing for Nanotechnologies,” In Proc.of 17th VLSI Design/CAD Symposium, pp. 707-710, Hualian, Taiwan, 11 Aug 2006.
[21] T.-C. Huang and L. Li,“IDDS Testing: A High-Resolution Current Test Scheme for Nanotechnologies,” Accepted, IEEE International Workshop on Current and Defect Based Test in conjunction with ITC, pp.25-28, Santa Clara, Oct 27, 2006.
[22] T.-C. Huang, G.-B. Chang and L. Li, “Congruence Synchronous Mirror Delay,” Submitted to ISCAS2007, Oct. 2006.
[23] Y.-W. Chao and T.-C. Huang, “A Low-Voltage Zigzag Supply-Gating Scheme for Wakeup Acceleration,” Submitted to IEEE Symp. on VLSI Circuit, Japan, 2007.
[24] T.-C. Huang, L. Li and Y.-W. Chao, “A Low-Power High-Speed Adaptive Super-Cutoff CMOS Logic Structure with High Current Testability,”Submitted to IEICE Transactions on Electronics, 2006.
[25] T.-C. Huang and L. Li, “A Fine-Grained Power-Gating Logic Cell Structure with Low Spike and High Current-Resolution,” ROC Patent, under application, 2006.
[26] S. Ghosh, S. Bhunia and K. Roy, “Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability,” Asian Test Symposium, pp. 404-409, 2005.
[27] TSMC Reference Flow 6.0, Taiwan Semiconductor Manufacturing Co., June 2005.
[28] TSMC Reference Design Flow 7.0, Taiwan Semiconductor Manufacturing Co., 17 July 2006.
[29] J.-C. Tzeng and T.-C. Huang, “Vector Control Technique and Sleep-Transistor Allocation for Supply-Gating Current Spike Reduction in Power Management,” In Proc. IEE Mobility Conference, Session 3-2A2, Guangzhou, China, 15 Nov 2005.
[30] T.-C. Huang, J.-C. Tzeng, Y.-W. Chao, Ji-Jan Chen, W.-T. Liu and K.-J. Lee, “A Supply-Gating Scheme for Both Data-Retention and Spike-Reduction in Power Management and Test Scheduling,” In Proc. IEEE Int’l Symp. on VLSI Design, Automation and Test, pp.167-170, Apr 2006.
[31] K. N. Laker and W.M.C. Sansen, Design of Analog Integrated Circuits and Systems. McGraw-Hill. 1994.
[32] C. Thibeault, “An Histogram Based Procedure for Current Testing of Action Defects,” In Proc. International Test Conf. ,pp. 714-723,1999.
[33] Y. Okuda, “DECOUPLE: Defect Current Detection In Deep Submicron IDDQ” ,In Proc. International Test Conf. ,pp. 199-206,2000.
[34] Hirase, J.; Goi, Y.; Tanaka, Y, “IDDQ Testing Method using a Scan Pattern for Production Testing,” Proceedings of the 14th Asian Test Symposium (ATS ’05), pp.18 – 21,2005.
[35] P. Maxwell, P O’Neil, A. Aitken, R. Dudley, N. Jaarsma, M. Ouach & D. Wiseman, “Current Ratios: A Self-Scaling Technique for Production IDDQ Testing,” In Proc. International Test Conf., pp. 738-746, 1999.