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研究生:何威毅
研究生(外文):Wei-Yi He
論文名稱:具輸出可觀測邏輯之隨機存取掃描法
論文名稱(外文):A Random Access Scan with Combinational Output Observable Logics
指導教授:黃宗柱
指導教授(外文):Tsung-Chu Huang
學位類別:碩士
校院名稱:國立彰化師範大學
系所名稱:電子工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:中文
論文頁數:52
中文關鍵詞:串列掃瞄隨機存取掃瞄尖峰功率效能衝擊測試向量測試資料量
外文關鍵詞:Serial ScanRandom Access ScanPeak PowerPerformance ImpactTest VectorTest Data Volume
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在超大型積體電路技術的發展下,電晶體密度與運算頻率的提升,使晶片測試領域面臨了巨大挑戰。為了增加晶片的可控制性與可觀測性,掃瞄技術是一種最廣為使用的測試方法。然而,此技術卻有大量的功率消耗與測試成本之嚴重問題。其中,測試成本又可概分為兩個主要因素:測試時間、測試資料量。
首先,在功率消耗方面,我們提出一項具輸出可觀測邏輯之技術,可以有效的降低尖峰功率的問題,並且在額外的多工邏輯輸出架構下,利用所提出之演算法來排序多工器的組合,使得延遲衝擊能夠進一步地改善約至80%。另外,尖峰功率平均上亦可減少約有57%。
再者,為了克服在測試時功率過高、資料量大與時間過長的問題,在本篇論文中,我們採取可同時減少上述問題的隨機存取掃瞄架構,發展可避免突波發生之新測試架構。其次,利用邏輯輸出技術,在擷取週期時能大量減少尖峰功率,並採納向量排序法與未定義位元填充技術應用於測試向量,使測試時間與資料量更加減少。我們並發展協助自動合成之軟體工具,將ISCAS89中的8個基準大電路合成佈局,且與相關參考文獻做比較。實驗的結果顯示,我們的架構不僅峰值功率平均可降低78%,測試時間與測試資料量則大約可分別降至64%與86%。另外,整體平均面積亦約略可省13%。
因此,嶄新的掃瞄架構不僅可有效的減少測試時間與測試資料量,亦克服許多相關論文所忽略的尖峰功率之議題。
With the progress of very large scale integration (VLSI) techniques, the increasing transistor density and operating speed have crucially challenged the test. For the sake of enhancing the controllability and observability of the circuit, scan technique is a widely used design of testability (DFT) method. However, excess power dissipation and large test cost are two critical problems of scan testing. The test cost is composed of two major factors: test application time and test data volume.
First, for the power consumption, we present a combinational output observable logics (COOL) technique to effectively reduce the peak power. And then, under this design with multiplexers (MUXs), the proposed algorithm is utilized by sorting MUXs so that the delay impact can be further improved to 80%. In addition, the peak power can also be decreased by 57% on average.
Furthermore, to overcome the issues on the peak power, test data volume and test application during testing, in the thesis we adopt the random access scan (RAS) architecture to simultaneously reduce the above issues for developing a novel hazard-free scan design. Using the COOL technique can reduce a lot of peak power during the capture cycle. And adopting the vector ordering and X-filling methods is applied to test generation for shortening test application time and test data volume. On the other hand, we also develop the automatic flow design to compare with the previous work in eight circuits of ISCAS89 benchmark. According to experimental results, the proposed design can not only reduce peak power by 78% but also shrink test application time and test data volume by 64% and 86% in average respectively. Besides, area overhead can be also saved by 13%.
Therefore, the proposed scan architecture can not only significantly reduce test application time and test data volume, but also solve the peak power issue that many previous works are neglected.
中文摘要 i
英文摘要 ii
誌謝 iii
目錄 iv
圖目錄 vi
表目錄 viii

第一章 緒論 1
1-1 動機 1
1-2 技術概要 2
1-3 論文架構 3

第二章 研究背景與相關文獻 4
2-1 研究背景 4
2-1-1 串列掃瞄 4
2-1-2 隨機存取掃瞄 6
2-2 相關文獻 8
2-2-1 測試功率 8
2-2-2 測試資料量、測試時間與測試接腳數目 12

第三章 具輸出可觀測邏輯之技術 15
3-1 基本概念 15
3-2 應用於具輸出可觀測邏輯技術之演算法 17
3-2-1 概要 17
3-2-2 第一種演算法:Huffman-like algorithm 20
3-2-3 第二種演算法:Reverse Huffman-like algorithm 23
3-2-3-1 Huffman-like algorithm之探討 23
3-2-3-2 改善因子 24
3-2-3-2 Reverse Huffman-like algorithm 27
3-3 實驗結果 30
3-4 結論 33

第四章 具輸出可觀測邏輯之隨機存取掃瞄法 34
4-1 具輸出可觀測邏輯之隨機存取掃瞄架構 34
4-1-1 RAS Cell設計 34
4-1-2 掃瞄輸出設計 38
4-1-3 COOL-RAS架構 42
4-2 測試向量的產生 44
4-3 實驗結果 48
4-4 結論 51

第五章 總結 52
參考文獻 53
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