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研究生:林政男
研究生(外文):Jeng-Nan Lin
論文名稱:多重閘極電晶體受雜散摻雜影響之分析
論文名稱(外文):Analysis of Discrete Dopant Impact on Multi-Gate MOSFETs
指導教授:江孟學
指導教授(外文):Meng-Hsueh Chiang
學位類別:碩士
校院名稱:國立宜蘭大學
系所名稱:電子工程學系碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:中文
論文頁數:98
中文關鍵詞:雜散摻雜效應臨界電壓汲極引致能障下降雙閘極電晶體鰭式電晶體
外文關鍵詞:Discrete dopant effectThreshold voltageDIBLDG MOSFETFinFET
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  本論文主要研究雜散摻雜效應對於先進元件的影響,透過學理分析與二維、三維數值模擬,深入探討極度微縮的金氧半場效電晶體通道內部原子化雜質的變動對於元件特性方面的影響。為了深入了解基本的物理意義,摻雜質原子變動的問題將會採用宏觀模型來做深入的探討。從二維模擬結果表現出極度微縮元件易受到雜散摻雜效應的影響,即使在一個未摻雜質的矽通道上,都有可能因為一個非預期雜質的座落,進一步造成元件特性上所不能接受的變化,因此如何有效的控制通道上摻雜將是有其必要性的,然而二維結構不能充分表現雜散摻雜效應的影響。利用實際三維結構的模擬結果可以更深入了解雜散摻雜效應對於元件特性的影響層面,結果顯示雜散摻雜效應造成元件特性的變動範圍並不如二維結構來得劇烈。並且從不同元件架構的比較得知三閘極電晶體在抑制短通道效應的表現相當優越,且具有較大的元件結構彈性。
  此外從先進元件結構的電位模型分析方面,本論文所採用的模型對於評估二維與三維的DG MOSFET矽通道內部電位有相當水準的準確性,然而受到上層閘極電場的影響,此模型並不適用於FinFET與三閘極電晶體。
  最後以實現與應用的觀點出發,利用非對稱閘極結構的三閘極電晶體,不僅在部分元件特性上的表現會優越於使用midgap材料的元件,甚至對於需要混合低功率消耗與高效能的積體電路而言,採用非對稱的閘極結構是非常適合的。
The thesis mainly focuses on discrete dopant impact in the advanced devices, and the impact is investigated via physical analyses and 2D & 3D numerical simulations. We analyze the fluctuation of atomization impurity in the channel and the influenced characteristics of the devices, especially for the extremely scaled devices. The issue of the impurity fluctuation has been approximated with macro-model in order to understand the basic physical meaning.
The results for 2D structure simulations show that the discrete dopant introduces significant impact on the characteristics of the extremely scaled devices. Even in an undoped si-channel, it could cause unacceptable fluctuation due to an unintended impurity dopant located in the channel. Hence how to control the impurity profile in the channel is necessary. However it couldn’t completely exhibit the discrete dopant effect using the 2D structures.
The device characteristics influenced by the discrete dopant could be better understood using true 3D structure simulations. Our results show that the degree of characteristics fluctuation is less than that from 2D structure simulations. In addition, from the comparison of different device structures using 3D simulation, the triple-gate MOSFET shows suppressed short channel effects, device dimension of which can be more flexible than that of double-gate MOSFET or FinFET.
In order to analyze electric potential in advanced structures, we use analytical model to estimate that 2D and 3D electric potential in silicon for DG MOSFET. But the model may not predict very accurate FinFET and tripe-gate MOSFET results due to additional top gate.
In the end, form the viewpoint of fabrication and application, tripe-gate MOSFET with asymmetry gate structure not only presents superiority to midgap material in device characteristics, but is also applicable to low-power and high-performance VLSI.
誌謝 I
摘要 II
Abstract III
目錄 V
圖目錄 VII
表目錄 XIII
Chapter 1 序論 1
1 - 1. 前言 1
1 - 1 - 1. 短通道效應 1
1 - 1 - 2. 多重閘極元件 2
1 - 2. 研究動機 4
1 - 3. 章節架構 6
Chapter 2 雜散摻雜效應對於多重閘極電晶體的影響 7
2 - 1. 多重閘極結構的模擬 7
2 - 1 - 1. 多重閘極結構上的定義 7
2 - 1 - 2. 雜散摻雜分佈的實現 10
2 - 1 - 2 - 1. 均勻摻雜與雜散摻雜對於元件特性的影響 13
2 - 1 - 2 - 2. 宏觀模型與微觀模型的比較 17
2 - 2. 雜散摻雜效應在二維結構上的影響 20
2 - 2 - 1. 受體雜質的雜散摻雜效應對於元件特性的影響 21
2 - 2 - 2. 施體雜質的雜散摻雜效應對於元件特性的影響 27
2 - 3. 雜散摻雜效應在三維結構上的影響 34
2 - 3 - 1. 雜散摻雜效應對於DG MOSFET元件特性的影響 34
2 - 3 - 2. 雜散摻雜效應對於FinFET元件特性的影響 42
2 - 3 - 3. 雜散摻雜效應對於三閘極電晶體元件特性的影響 45
2 - 4. 雜散摻雜效應在並聯元件上的影響 48
2 - 4 - 1. 雜散摻雜效應對於二維結構的元件並聯之影響 49
2 - 4 - 2. 雜散摻雜效應對於三維結構的元件並聯之影響 51
Chapter 3 先進元件的電位模型分析 54
3 - 1. 二維電位模型的推導 54
3 - 2. 模型分析與模擬結果的比較 57
Chapter 4 非對稱閘極的三閘極電晶體之探討 63
4 - 1. 非對稱閘極的結構設計 63
4 - 2. 非對稱閘極結構特性之分析 64
4 - 3. 非對稱閘極結構特性之應用 68
Chapter 5 結論 70
Appendix A 二維電位模型的推導 72
References 78
[1] 施敏原著,黃調元譯, “半導體元件物理與製程技術 (第二版),” 國立交通大學出版社, 2002.
[2] Michael Quirk與Julian Serda著, 劉文超與許渭州校閱, 羅文雄、蔡榮輝與鄭岫盈譯, “半導體製程技術,” 台灣培生教育出版股份有限公司, 2004.
[3] N. Yamauchi, K. Kato and T. Wada, “Channel edge doping (CED) method for reducing the short-channel effect,” IEEE Electron Device Letters, vol. 4, no. 11, Nov. 1983, pp. 406-408.
[4] Stephen Sleva and Yuan Taur, “ The influence of source and drain junction depth on the short-channel effect in MOSFETs,” IEEE Trans. Electron Devices, vol. 52, no. 12, Dec. 2005, pp. 2814-2816.
[5] T. Ghani, K. Mistry, P. Packan, S. Thompson, M. Stettler, S. Tyagi and M. Bohr, “Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors,” IEEE VLSI Digest of Technical Papers, Jun. 2000, pp. 174-175.
[6] K. KONRAD YOUNG, “Short-Channel Effect in Fully Depleted SOI MOSFET’s,” IEEE Trans. Electron Devices, vol. 36, no. 2, Feb. 1989, pp. 399-402.
[7] Xiaoping Liang and Yuan Taur, “A 2-D Analytical Solution for SCEs in DG MOSFETs,” IEEE Trans. Electron Devices, vol. 51, no. 8, Aug. 2004, pp. 1385-1391.
[8] Tze-Neng Lin, “Analyses of the Multi-Gate MOSFET Characteristics,” Master thesis, National Ilan Univ., Ilan, Taiwan, R.O.C., 2006.
[9] Asen Asenov, “Random Dopant Induced Threshold Voltage Lowering and Fluctuations in Sub-0.1 μm MOSFET’s: A 3-D “Atomistic” Simulation Study,” IEEE Trans. Electron Devices, vol. 45, no. 12, Dec. 1998, pp. 2505-2513.
[10] A. Asenov, “Efficient 3D ‘Atomistic’ Simulation Technique for Studying of Random Dopant Induced Threshold Voltage Lowering and Fluctuations in Decanano MOSFETs,” Computational Electronics, 1998. IWCE-6, Extended Abstracts of 1998 Sixth International Workshop, Oct. 1998, pp. 263-266.
[11] Shuichi Toriyama, Daisuke Hagishima, Kazuyz Matsuzawa and Nobuyiki Sano, “Device Simulation of Random Dopant Effects in Ultra-small MOSFETs Based on Advanced Physical Models,” IEEE SISPAD, Sept. 2006, pp. 111-114.
[12] Yuan Taur and Tak H. Ning, “Fundamentals of modern VLSI devices,” Cambridge, 1998.
[13] Meng-Hsueh Chiang, Cheng-Nang Lin and Guan-Shyan Lin, “Threshold voltage sensitivity to doping density in extremely scaled MOSFETs,” Semiconductor Science and Technology, Jan. 2006, pp. 190-193.
[14] International Technology Roadmap for Semiconductors, 2004. Online: http://public.itrs.net/.
[15] Ji-Woon Yang and Jerry G. Fossum, “On the Feasibility of Nanoscale Triple-Gate CMOS Transistors,” IEEE Trans. Electron Devices, vol. 52, no. 6, Jun. 2005, pp. 1159-1164.
[16] Taurus Process & Device User Manual Version 2002.4, Feb. 2003.
[17] Taurus Medici Taurus Device User Guide Version X-2005.10, Oct. 2005.
[18] Yasuhisa Omura, Seiji Horiguchi, Michiharu Tabe and Kenji Kishi, “Quantum-Mechanical Effects on the Threshold Voltage of Ultrathin-SOI nMOSFET’s,” IEEE Electron Device Letters, vol. 14, no. 12, Dec. 1993, pp. 569-571.
[19] H. Mahima, H. Lshikuro and T. Hiramoto, “Threshold Voltage Increase by Quantum Mechanical Narrow Channel Effect in Ultra-Narrow MOSFETs.” IEEE IEDM, Dec. 1999, pp. 379-382.
[20] E. Gnani, S. Reggiani, M. Rudan, G. Baccarani, “A Quantum-Mechanical Analysis of the Electrostatics in Multi-Gate FETs,” IEEE SISPAD, Sept. 2005, pp. 291-294.
[21] A. Asenov, G. Slavcheva, A. R. Brown, J. H. Davies and S. Saini, “Quantum Mechanical Enhancement of the Random Dopant Induced Threshold Voltage Fluctuations and Lowering in Sub 0.1 micron MOSFETs,” IEEE IEDM, Dec. 1999, pp. 535-538.
[22] Asen Asenov, Gabriela Slavcheva, Andrew R. Brown, John H. Davies and Subhash Saini, “Increase in the Random Dopant Induced Threshold Fluctuations and Lowering in Sub-100 nm MOSFETs Due to Quantum Effects: A 3-D Density-Gradient Simulation Study,” IEEE Trans. Electron Devices, vol. 48, no. 4, Apr. 2001, pp. 722-729.
[23] Xinghai Tang, Vivek K. De and James D. Meindl, “Intrinsic MOSFET Parameter Fluctuations Due to Random Dopant Placement,” IEEE Trans. VLSI systems, vol. 5, no. 4, Dec. 1997, pp. 369-376.
[24] Nobuyuki Sano, Kazuya Matsuzawa, Mikio Mukai and Noriaki Nakayama, “Role of Long-Range and Short-Range Coulomb Potentials in Threshold Characteristics under Discrete Dopants in Sub-0.1 um Si-MOSFETs,” IEEE IEDM, Dec. 2000, pp. 275-278.
[25] Tatsuya Ezaki, Takeo Ikezawa, Akio Notsu, Katsuhiko Tanaka and Masami Hane, “3D MOSFET Simulation Considering Long-Range Coulomb Potential Effects for Analyzing Statistical Dopant-Induced Fluctuations Associated with Atomistic Porcess Simulator,” IEEE SISPAD, Sept. 2002, pp. 91-94.
[26] H. Shang, L. Chang, X. Wang, M. Rooks, Y. Zhang, B. To, K. Babich, G. Totir, Y. Sun, E. Kiewra, W. Haensch, “Investigation of FinFET devices for 32nm technologies and beyond,” IEEE VLSI Digest of Technical Papers, 2006 , pp. 54-55.
[27] Xiaoping Liang, “Analytical Modeling of Short Channel Effects in Double Gate MOSFET,” Ph.D. dissertation, University of California, San Diego, CA, U.S.A., 2006.
[28] Jack Kavalieros, Brian Doyle, Suman Datta, Gilbert Dewey, Mark Doczy, Ben Jin, Dan Lionberger, Matthew Metz, Willy Rachmady, Marko Radosavljevic, Uday Shah, Nancy Zelick and Robert Chau, “Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering,” IEEE VLSI Digest of Technical Papers, 2006, pp. 50-51.
[29] Tsung-Yang Liow, Kian-Ming Tan, Rinus T. P. Lee, Anyan Du, Chih-Hang Tung, Ganesh S. Samudra, Won-Jong Yoo, N. Balsubramanian and Yee-Chia Yeo, “Strained N-Channel FinFETs with 25 nm Gate Length and Silicon-Carbon Source/Drain Regions for Performance Enhancement,” IEEE VLSI Digest of Technical Ppers, 2006, pp. 56-57.
[30] Hyunjin Lee, lee-Eun Yu, Seong-Wan Ryu, Jin-Woo Han, Kanghoon Jeon, Dong-Yoon Jang, Kuk-Hwan Kim, Jiye Lee, Ju-Hyun Kim, Sang Cheol Jeon, Gi Seong Lee, Jae Sub Oh, Yun Chang Park, Woo Ho Bae, Hee Mok Lee, Jun Mo Yang, Jung Jae Yoo, Sang Ik Kim and Yang-Kyu Choi, “Sub-5nm All-Around Gate FinFET for Ultimate Scaling,” IEEE VLSI Digest of Technical Papers, 2006, pp. 58-59.
[31] David J. Frank, Yuan Taur and Hon-Sum P. Wong, “Generalized Scale Length for Two-Dimensional Effects in MOSFET’s,” IEEE Electron Device Letters, vol. 19, no. 10, Oct. 1998, pp. 385-387.
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