|
Reference Chapter 1: [1.1] D.Kahng and S.M.Sze, ”A Floating Gate and Its Application to Memory Device,” Bell Syst. Tech., 46,1283(1967) [1.2] “Advanced Memory Technology and Architecture”, short course, IEDM 2001 [1.3] T. Ohnakado, H. Onada, O. Sakamato, K. Hayashi, N. Nishioka, H. Takada, K. Sugahara, N. Ajika and S. Satoh, “Device characterisitics of 0.35μm P-channel DINOR flash memory using band-to-band tunneling-induced hot electron (BBHE) programming”, IEEE Trans. Electron Device, Vol 46, pp 1866-1871, 1999. [1.4] T.P.Ma, “Marking silicon nitride film a viable gate dielectric”, IEEE Trans. Electron Device, 45(3), pp 680-690, 1998. [1.5] Flash Memories , edited by P. Cappelletti et al., Kluwer Acadenic Publishers, 1999 [1.6] R-L. Lin, Y.-S. Wang and Chairs C-H Hsu, “Muti-level P-channel flash memory”, The 5th International Conference on Solid-State and Integrated Circuit Technology, pp. 457, 1998. [1.7] D. Forhman-Bentchkowsky, “Memory behavior in a floating-gate avalanche-injection MOS(FAMOS) structure”, Appl. Phy. Lett., vol. 18,pp 332-334, 1971. [1.8] --,“FAMOS-A new Semiconductor charge storage device”, Solid State Electron., vol. 17,pp. 517-520, 1974. [1.9] V. N. Kynett, A. Baker, M. Fandrich, G. Hoekstra, O. Jungroth, J Kreifels, and S. Wells, “An in-system reprogrammable 256K CMOS Flash memory2,” in ISSCC Conf. Proc., 1988, pp.132-133. [1.10] F. Masuoka, M. Momodomi, Y. Iwata, and R. Shirota, “New ultra high density EPROM and Flash with NAND structure cell,” in IEDM Tech. Dig., 1987, pp.552-555. [1.11] S. Aritome, “Advance Flash memory technology and trends for file storage application,” in IEDM Tech Dig., 2000, pp. 763-766. [1.12] S. Lai, “Flash memories: Where we were and where we are going,” in IEDM Tech. Dig., 1998, pp. 971-973. [1.13] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, “Flash memory cell—An overview,” Proc. IEEE, vol. 85, pp 1248-1271, Aug. 1997. [1.14] P. Pavan and R. Bez, “The industry standard Flash memory cell in Flash memories,” P. Cappelletti et al., Ed. Norwell, MA: Kluwer, 1999. [1.15] P. Cappelletti, C. Golla, P. Olivo, E. Zanoni, “Flash Memories”, Kluwer Academic, Norwell, 2000. [1.16] KUWANO Masajiko, ”Memory IC,” CQ, Tokyo, 2001. [1.17] TOSHIBA America Electronics Components, “NAND vs NOR Flash Memory Technology Overview.” [1.18] A. Thean and J. P. Leburton, “Flash memory: towards single-electronics,” IEEE, Oct 2002. [1.19] International Technology Roadmap For Semiconductors 2006 Update. [1.20] Y. S. Shin, “Non-volatile Memory Technologies for Beyond 2010”, Symposium on VLSI Circuits Digest of Technical Papers, 2005, pp.156-159. [1.21] S. Tiwari, F. Rana, K. Chan, H. Hanafi, W. Chan, and Doug Buchanan, “Volatile adn non-volatile memories in silicon with nano-crystal storage,” IEDM Tech. Dig., pp.521-524 Dec. 1995. [1.22] Y. Yang, A. Purwar, and M. H. White, “Reliability considerations in scaled SONOS nonvolatile memory device,” Solid-State Electronics, vol.43, pp.2025-2032, May 1999. [1.23] Z. Liu, C. Lee, V, Narayanan, G. Pei, and E.C Kan, IEEE Tran. Electron Device 49, 1606, 2002. [1.24] Y. C. King, T. J. King, and C. Hu, IEEE Trans. Electron Device, 48, 2001, pp696. [1.25] F. K. LeGoues, Rosenberg, T. Nguyen, F. Himpsel, and B.S. Meyerson, J. Appl. Phys., 65, 1724, 1989. [1.26] J. Eugene, F. K. LeGoues, V.P.Kesan, S.S. Iyer, and F. M. d’Heurle, Appl. Phys. Lett., 59 78, 1991. [1.27] J. J. Lee, X. Wang, W. Bai, N. Lu, and D. L. Kwong, IEEE Trans. Electron Devices, ”Theoretical and experimental investigation of Si nanocrystal memory device with HfO2 high-k tunneling dielectric,” 50, 2067, 2003. [1.28] I. Kim, S. Han, H. Kim, J. Lee, B. Choi, S. Hwang, D. Ahn, and H. Shin, IEEE Int. Electron Device Meeting Tech. Dig., 1998, pp.111-114. [1.29] A. Fernandes, B. DeSalvo, T. Baron, J. F. Damlencourt, A. M. Papon, D. Lafound, D. Mariolle, B. Guillaumot, P. Besson, G. Ghibaudo, G. Pananakakis, F. Martin, and S. Haukka, IEEE Int. Electron Device Meeting Tech. Dig., 2001, pp. 155-158. [1.30] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal nanocrystal memories-partⅡ: electrical characteristics,” IEEE Trans. Electron Device, 49, 1614, 2002. [1.31] S. Baik and K.S.Lim, Appl. Phys. Lett., 81, 5186, 2002. [1.32] S.P. Murarka, “Silicides for VLSI applications”, Academic Press, INC., London, 1983, pp3-4 [1.33] S.K.Samanta, P.K. Singh, Won Jong Yoo, Ganesh Samudra, Yee-Chia Yeo, L. K. Bera, and N. Balasubramanian, ”Enhancement of Memory Window in short Channel Non-Volatile Memory Device Using Double Layer Tungsten Nanocrystal”, IEEE, 2005
Chapter 2 :
[2.1] James D. Plummer, Micharl D. Deal, Peter B. Griffin,” Silicon VLSI Technology: Fundamental, Practice and Modeling”, Prentice Hall, 2003. [2.2] www.lasurface.com/database, ref.111. [2.3] www.lasurface.com/database, ref 13, 111, 150. [2.4] M. KATOH and T. TAKBDA, ”Chemical State Analysis of Tungsten and Tungsten Oxides Using an Electron Probe Microanalyzer,” J. J. Appl. Phy, Vol 43, No 10, 2004, pp. 7297-7295 [2.5] H. QIU and Y. F. LU, “Scanning Tunneling Microscopy and Atomic Force Microscopy Studies of Laser Irradiation of Amorpgous WO3 Thin Films”, J.J. Appl. Phys, Vol. 39, 2000, pp.5889-5893. [2.6] S.P. Murarka, “Silicides for VLSI applications”, Academic Press, INC., London, 1983. [2.7] Robert Beyers, “Thermodynamic considerations in refractory metal-silicon-oxygen systems”, J. Appl. Phys., 56(1), 1 July 1984, pp147-152. [2.8] S. Zirinsky, W. Hammer, F d’Herurle, and J. Baglin, “Oxidation mechanism in WSi2 thin films”, Appl. Phys. Lett. 33(1), 1 July 1978, pp76-78. [2.9] S. M. Sze, Kwok k. NG, “Physic of Semiconductor Device”, Wiley, New Jersey, 2007, pp350-356.
Chapter 3:
[3.1] E. C. Carr and R.A. Buhrman, “Role of interfacial nitrogen in improving thin silicon oxide grown in N2O,” Appl. Phys. pp.54-56 [3.2] U. sharma, R. Moazzami, P. Tobin, Y. Okada, S. K. Cheng and J. Yeargain, “Vertical Scaled High Reliability EEPROM Device with Ultra-thin Oxynitride Film Prepared by RTP in N2O/O2 Ambient,” IEEE IEDM, Tech. Dig., 1992, pp 461-464 [3.3] P. J. Tobin, Yoshio Okada, Sergio A. Ajuria, Vikas Lakhotia, W. A. Feil, and R. I. Hedge. “Furnace formation of silicon oxynitride thin dielectrics in nitrous oxide (N2O): The role of nitric oxide (NO)”, J. Appl. Phys 75(3), 1994 Feb, pp1881-1817. [3.4] C. Tsamis, D.N. Kouvatsos, and D. Tsoukalas, “Influence of N2O oxidation of silicon on point defect injection kinetics in the high temperature regime”, Appl. Phys. Lett., 69(18), 28 October 1996, pp2725-2727 [3.5] J. Kim, J. D. Choi, W. C. Shin, D. J. Kim, H. S. Kim, K. Mang, S. T. Ahn and O. H. Kwon, ”Scaling Down of Tunnel Oxynitride in NANS Flash Memory: Oxynitride Selection and Raliability”, IEEE, 1997 [3.6] M. Kato, N. Miyamoto, H. Kume, A. Satoh, T. Adachi, M. Ushiyama and K. Kimura, “Read-Disturb Degradation Mechanism due to Electron Trapping in the Tunnel Oxide for Low-Voltage Flash Memories,” IEEE IEDM, Tech, Dig., 1994, pp. 45-48. [3.7] J. De Blauwe, J. Van Houdt, D. Wellekens, R. Degraeve, Ph. Roussel, L. Haspeslagh, L. Deferm, G. Groeseneken and H. E. Maes, “A New quantitative model to predict SILC-related disturb characteristics in Flash EEPROM devices,” IEEE IEDM, Tech. Dig., 1996, pp343-346.
Chapter 4: [4.1] E. C. Carr and R.A. Buhrman, “Role of interfacial nitrogen in improving thin silicon oxide grown in N2O,” App. Phys. pp.54-56 [4.2] P. J. Tobin, Yoshio Okada, Sergio A. Ajuria, Vikas Lakhotia, W. A. Feil, and R. I. Hedge. “Furnace formation of silicon oxynitride thin dielectrics in nitrous oxide (N2O): The role of nitric oxide (NO)”, J. Appl. Phys 75(3), 1994 Feb, pp1881-1817.
Chapter 5:
[5.1] P. T. Liu, C. T. Tsai, T. C. Chang, K. T. Kin, P. L. Chang, IEEE Trans. Nanotech., 6(1), 29 (2007). [5.2] P.T. Liu, C.T Tsai, P.Y. Yang, “Effects of supercritical CO2 fluid on sputter-deposited hafnium oxide”, Appl 90, 223101, 2007 [5.3] T. Sameshima, K. Sakamoto, Y. Tsunoda, and T. Saitoh, Jap. J. Appl. Phys., 37(2, 12A), L1452 (1998). [5.4] M. Kunii, Jap. J. Appl. Phys., 45(2A), 660 (2006).
|