在大型的控制器資料路徑系統 (controller-datapath System) 當中，資料路徑的交換動作 (switching activity) 是由控制單元所掌控，非必要性的資料交換動作會造成更多的功率消耗， 因此控制單元 (controller) (亦即有限狀態機，Finite State Machine) 的設計將會影響到系統整體的功率消耗。狀態指派 (state assignment) 和輸出編碼 (output encoding) 是在控制單元的硬體實現中影響系統功率的兩大因素，在這篇論文中，我們提出了一個整數線性規劃 (integer linear programming, ILP) 的方法來解決狀態指派和輸出訊號編碼的問題，其目的是要減少資料交換動作以達到功率最佳化的目標。在時序和資源限制 (timing and resource constraints) 之下，此方法不需要重新排程資料路徑的運算而且沒有額外的面積負擔。為了驗證我們所提出的整數線性規劃方法的效能，我們使用這個方法實作數個控制器資料路徑系統。實驗結果顯示我們的技術與只最佳化面積而不考慮功率的傳統工具SIS相比較平均可以達到30.513%的功率節省。除了可以確實達到顯著的系統功率節省，我們提出的方法亦不會造成額外的面積負擔。

In large controller-datapath systems, the switching activity of datapath is administered by controller. The unnecessary switching activity will cause more power consumption, and therefore the design of controllers (i.e. Finite State Machines, FSMs) will influence the whole power consumption of the systems. The state assignment and output encoding are the two major factors influencing the power of system under the hardware implementation of controllers. In this paper, we present an integer linear programming (ILP) method to solve the state assignment and output encoding problems. The purpose is to reduce switching activity such that the goal of power optimization can be achieved. It has not to reschedule the operations of datapath under timing and resource constraints and has no extra area overhead. In order to verify the effectiveness of our proposed ILP approach, we use this approach to implement several controller-datapath systems. Experimental results show that our proposed approach achieves an average of 30.513% power savings compared to the traditional area optimal synthesis tool, SIS, where power is not considered. Our proposed approach does not cause extra area overhead while achieving a significant power saving of systems.

CHAPTER 1 INTRODUCTION 1
1.1 Motivation 1
1.2 Low Power Design Approaches 1
1.2.1 State Assignment 2
1.2.2 Output Encoding 2
1.2.3 Integrated Approach 3
1.3 Paper Organization 3
CHAPTER 2 RELATED WORK 5
2.1 Related Research 5
2.2 Problem Description 6
2.3 Integer Linear Programming (ILP) Solver (Lingo) 7
2.4 KISS2 Format 9
2.5 System for Sequential Circuit Synthesis Tool (SIS) 11
CHAPTER 3 ILP FORMULATION 12
3.1 Definitions 13
3.2 Constraints 17
3.3 Objective Function 18
3.4 Design Flow 19
CHAPTER 4 CONTROLLER-DATAPATH SYSTEMS 24
4.1 Controller-Datapath Architecture and Graph Model 24
4.1.1 GCD 24
4.1.2 DIFF 26
4.1.3 SODF 28
4.1.4 Shift Multiplier 31
4.1.5 FOWDF 33
4.1.6 AR Lattice Filter 35
4.2 Next State and Output Table of Controller 37
4.2.1 GCD 37
4.2.2 DIFF 39
4.2.3 SODF 41
4.2.4 Shift Multiplier 43
4.2.5 FOWDF 44
4.2.6 AR Lattice Filter 47
4.3 Complexity of Output Encoding 48
4.3.1 GCD 49
4.3.2 DIFF 49
4.3.3 SODF 49
4.3.4 Shift Multiplier 50
4.3.5 FOWDF 50
4.3.6 AR Lattice Filter 51
CHAPTER 5 EXPERIMENTAL RESULTS 52
5.1 GCD 54
5.2 DIFF 55
5.3 SODF 56
5.4 Shift Multiplier 57
5.5 FOWDF 58
5.6 AR Lattice Filter 59
CHAPTER 6 CONCLUSION AND FUTURE WORK 60
6.1 Conclusion 60
6.2 Future Work 60
References 61

[1]B. Lin and A. R. Newton, “Synthesis of multiple-level logic from symbolic high-level description languages,” Proc. IFIP Int. Conf. Very Large Scale Integration, pp. 187-196, Aug. 1989.
[2]S. Devadas, H-K. T. Ma, A. R. Newton, and A. Sangiovanni-Vincentelli, “MUSTANG: State assignment of finite state machines targeting multilevel logic implementations,” IEEE Trans. Computer-Aided Design, vol. 7, pp. 1290-1300, Dec. 1988.
[3]X. Du, G. Hactel, B. Lin, and A. R. Newton, “MUSE: A multilevel symbolic encoding algorithm for state assignment,” IEEE Trans. Computer-Aided Design, vol. 10, pp. 28-38, Jan. 1991.
[4]T. Villa and A. Sangiovanni-Vincentelli, “NOVA: State assignment of finite state machines for optimal two-level logic implementation,” IEEE Trans. Computer-Aided Design, vol. 9, no. 9, pp. 905-924, sep. 1990.
[5]L. Benini and G. De Micheli, “State Assignment for Low Power Dissipation,” IEEE Journal for Solid-State Circuits, vol. 30, no. 3, pp. 32-40, March 1995.
[6]L. Benini, G. De Micheli, and F. Vermulen, “Finite State Machine Partitioning for Low Power,” Proc. International Symposium on Circuits and Systems, pp. 5-8, 1998.
[7]J. C. Monterio and A. L. Oliveria, “Finite State Machine Decomposition for Low Power,” Proc. Design Automaton Conference, pp. 758-763, 1998.
[8]E. Olson and S. Kang, “Low-Power State Assignment for Finite State Machines,” Proc. International Symposium on Low Power Design, pp. 63-68, 1994.
[9]C. Y. Tsui, M. Pedram, and A. Despain, “Low-Power State Assignment Targeting Two and Multilevel Implementations,” IEEE Trans. on CAD, vol. 17, pp. 1281-1291, 1998.
[10]A. Raghunathan, S. Dey, N. K. Jha, and K. Wakabayashi, "Power management for control-flow intensive designs," Tech. Rep. 96-C050- 4-5016-7, NEC C&C Research Labs, Princeton, NJ, Oct. 1996.
[11]K. S. Khouri, G. Lakshminarayana, and N. K. Jha, “High-level synthesis of low-power control-flow intensive circuits,” IEEE Trans. Computer-Aided Design, vol. 18, pp. 1715-1729, Dec. 1999.
[12]Jiong Luo, Lin Zhong, Yunsi Fei, and Niraj K. Jha, “Register binding-based RTL power management for control-flow intensive designs,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 23, issue 8, pp. 1175-1183, Aug. 2004.
[13]X. Tang, T. Jiang, A. Jones, and P. Banerjee, “Behavioral Synthesis with power Estimation and Optimization for Unscheduled Data-Dominated Circuits,” Journal of Low Power Electronics, vol. 1, no.3, pp. 259-272, Dec. 2005.
[14]U. Narayanan et. all., “Low Power Multiplexer Decomposition,” IEEE Symposium on Low Power Electronics and Design (ISLPED), 1997.
[15]K. Kim, T. Ahn, S.-Y. Han, C.-S. Kim and K.-H. Kim, “Low-power multiplexer decomposition by suppressing propagation of signal transitions," Proc. of IEEE Int. Symp. on Circuits and Sys. 2001, vol. 5, pp. 85-88, IEEE Press, 2001.
[16]D. Chen and J. Cong, “Register Binding and Port Assignment for Multiplexer Optimization,” Asian Pacific Design Automation Conf., Jan. 2004.
[17]R. K. Gupta and J. Li, “Control optimization using behavioral don’t cares,” Proc. IEEE Int. Symp. Circuits and Systems, 1996
[18]S. Mitra, L.J. Avra and E.J. McCluskey, “An Output Encoding Problem and a Solution Technique,” IEEE Trans. Computer-Aided Design, vol. 18, no. 6, pp. 761-768, June 1999.
[19]S. Chattopadhyay and P.N. Reddy, “Finite state machine state assignment targeting low power consumption,” IEE Proc., Comput. Digit. Tech., vol. 151, issue 1, pp. 61-70, 2004.
[20]A. Raghunathan, S. Dey, N.K. Jha, and K. Wakabayashi, “Controller re-specification to minimize switching activity in controller/data path circuits,” Proc. Int. Symp. on Low Power Electronics and Design, pp. 301-304, Aug. 1996.
[21]Kris Thornburg, Anne Hummel, “LINGO 8.0 TUTORIAL.”
[22]E. M. Sentovich et. al., “SIS: A System for Sequential Circuit Synthesis.” Dept. of Electrical Engineering and Computer Science, University of California, Berkeley, USA, Technical Report CA 94720,1992.
[23]P.G. Paulin, J.P. Knight, and E.F. Girczyc, “HAL: A Multi-Paradigm Approach to Automatic Data Path Synthesis,” Proc. 23rd IEEE/ACM Design Automation Conf. (DAC ''86), pp. 263-270, 1986.
[24]David A. Patterson and John L. Hennessy, Computer Organization & Design: The Hardware/Software Interface, 2nd edition, Morgan Kaufman Publisher, Inc.