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研究生:陳俊楠
研究生(外文):Chun-nan Chen
論文名稱:65奈米金氧半場效電晶體受製程與機械應力下之電性分析
論文名稱(外文):Electrical Analysis of 65nm MOSFETs under Process and Mechanical Stress
指導教授:翁�皒q
指導教授(外文):Herng-Yih Ueng
學位類別:碩士
校院名稱:國立中山大學
系所名稱:電機工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:中文
論文頁數:76
中文關鍵詞:低溫應變矽機械應力
外文關鍵詞:low temperaturestrained siliconmechanical bending
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近年來,為了提昇金氧半場效電晶體工作頻率及性能,尺寸不斷微縮,讓相同面積晶片可以擁有更多的電晶體數量。但微影技術已經接近瓶頸,所以我們必須另外尋找能夠提升電晶體效能的方法,應變矽就是目前提升電晶體性能最熱門的方法。在此論文裡,我們探討當金氧半場效電晶體通道受到製程應力或外加機械應力產生應變矽後的電性變化。
為了讓通道產生應變,在製程上若在NMOS上沉積Si3N4或PMOS採用矽鍺磊晶於源/汲結構,通道受到單軸應力,大幅提升NMOS及PMOS電性;另外,我們設計出可使用外加機械應力來彎曲矽基板,讓NMOS受到單軸張應力及PMOS通道受到單軸壓應力,此方法亦成功提高NMOS及PMOS汲極電流與載子移動率,提升程度和製程應力相當,兩種方法,都能有效提升MOSFET電性;此外,本論文並探討應變矽在低溫時,不同散射機制對電性的影響。
In recent years, in order to promote the MOSFET’s frequency and performance, the dimension keeping scale down, we can get more transistors in the same area. But nowadays the development of the lithography technology has come to the bottleneck, we must find the other way to improve the performance of transistor. In this study, the strained silicon effect and reliability of CMOS are fully discussed.
In order to get strain from the channel, by process, deposit Si3N4 at NMOS and adopt the silicon-germanium epitaxy on source/drain by PMOS, can effective improve NMOS and PMOS electronic characteristic. Besides, silicon substrate is bent by applying external mechanical stress, the lattice of channel will have strain due to uniaxial tensile stress by NMOS and strain due to uniaxial compressive stress by PMOS. By these ways, we successfully improve drain current and mobility of NMOS and PMOS.
Furthermore, this study is also probing into strain silicon at low temperature, the impacts on electronic characteristic by different scattering mechanism.
目錄.....................................................Ⅰ
表目錄.................................................Ⅳ
圖目錄.................................................Ⅴ
中文摘要............................................ VIII
英文摘要............................................. IX

第一章 緒論
1-1.電晶體發展簡介...............................1
1-2.研究動機...........................................2
1-3.文獻回顧...........................................3
1-4.本文結構...........................................6
第二章 理論基礎
2-1.應變矽的分類 ...................................7
2-1-1. 製程單軸伸張/壓縮應力..............7
2-1-2. 製程雙軸伸張/壓縮應力..............7
2-2. 應變矽電子特性...............................9
2-3.低溫電子特性...................................11
2-4金氧半場效電晶體原理....................12
第三章 實驗儀器與參數粹取
3-1. 實驗步驟........................................13
3-1-1. 實驗前準備.............................13
3-1-2. Sample研磨...........................13
3-1-3. 量測設定.................................14
3-2. 參數萃取........................................16
3-3. 實驗儀器........................................18
3-3-1. 研磨機台..................................18
3-3-2. 量測機台..................................18
第四章 結果與討論
4-1. 製程應力對電性的影響..................19
4-1-1. 氮化矽應力層對NMOS電性的影響.................19
4-1-2. 矽鍺源極/汲極結構對PMOS電性的影響............20
4-2. 機械研磨的影響................................21
4-3. 彎曲對電性的影響..........................22
4-3.1 室溫機械彎曲.................................22
4-3.2 NMOS機械彎曲..............................23
4-3.2 PMOS機械彎曲...............................23

4-4.低溫低溫機械彎曲.............................25
4-4-1 低溫壓縮彎曲.................................25
4-4-2 低溫伸張彎曲..................................26
第五章 結論與未來展望
結論與未來展望.........................................28

參考文獻.....................................................29

表目錄
表2-1 NMOS與PMOS通道受到不同應力對驅動電流的影響........37
表4-1 有無氮化矽應力對NMOS(W=1μm、L=1um)參數比較表....37
表4-2 有無氮化矽應力對NMOS(W=1μm、L=70nm)參數比較表....37
表4-3 有無矽鍺源汲極應力對PMOS(W=1μm、L=1um)參數比較表38
表4-4 有無矽鍺源汲極應力PMOS(W=1μm、L=70nm)參數比較表..38
表4-5 外加機械應力對NMOS(W=1μm、L=1um)之參數比較表. ...39
表4-6 外加機械應力對PMOS(W=1μm、L=1um)之參數比較表.... 39

圖目錄
圖1-1 Intel摩爾定律.....................................40
圖2-1 NMOS單軸伸張與PMOS單軸壓縮結構示意圖...............41
圖2-2 NMOS單軸伸張與PMOS單軸壓縮通道TEM示意圖.........41
圖2-3 雙軸伸張壓縮結構示意圖.............................42
圖2-4 (001)面上二重與四重簡併態的電子特性..............42
圖2-5 PMOS受應力價電帶E-K圖............................43
圖2-6 MOSFET透試圖......................................43
圖3-1研磨機.............................................44
圖3-2量測平台...........................................44
圖3-3量測機台...........................................45
圖3-4. 低溫平台..........................................45
圖4-1圖4-1 (a)標準電晶體與(b)源極/汲極端加上矽鍺磊晶電晶體示意圖.............................................46
圖4-2 有無氮化矽應力層NMOS(W=1μm、L=1μm)VG-NID曲線... 46
圖4-3 有無氮化矽應力層NMOS(W=1μm、L=70nm)VG-NID曲線... 47
圖4-4有無氮化矽應力層對NMOS(W=1μm、L=1μm)VG-gm曲線.. 47
圖4-5有無氮化矽應力層對NMOS(W=1μm、L=70nm)VG-gm曲線.. 48
圖4-6 矽鍺源/汲極電晶體製造方法簡單示意圖................48
圖4-7 有無矽鍺源汲極應力PMOS(W=1μm、L=1μm)VG-NID曲線.49
圖4-8 有無矽鍺源汲極應力PMOS(W=1μm、L=70nm)VG-NID曲線.49
圖4-9 有無矽鍺源汲極應力PMOS(W=1μm、L=1μm)VG-gm曲線....50
圖4-10 有無矽鍺源汲極應力PMOS(W=1μm、L=70nm)VG-gm曲線.50
圖4-11 NMOS 研磨前後之比較(W=10μm、L=70nm)..............51
圖4-12 PMOS 研磨前後之比較(W=10μm、L=70nm)..............51
圖4-13 伸張應力之模具....................................52
圖4-14 壓縮應力之模具....................................52
圖4-15不同彎曲曲率NMOS載子移動率(W=1μm、L=1μm)........53
圖4-16不同彎曲曲率PMOS載子移動率(W=1μm、L=1μm).......53
圖4-17伸張彎曲對NMOS VG-NID 曲線(W=1μm、L=1μm )........54
圖4-18壓縮彎曲對PMOS VG-NID 曲線(W=1μm、L=1μm ).........54
圖4-19壓縮彎曲對矽鍺源汲極PMOS VG-NID 曲線(W=1μm、L=1μm)55
圖4-20 低溫實驗流程圖....................................56
圖4-21 溫度對雜質與晶格散射影響..........................56
圖4-22 標準PMOS壓縮彎曲在低溫與室溫VG-NID 曲線...........57
圖4-23 SiGe S/D結構PMOS壓縮彎曲在低溫與室溫VG-NID 曲線....57
圖4-24 標準PMOS壓縮彎曲在不同溫度載子遷移率.............58
圖4-25 SiGe S/D結構PMOS壓縮彎曲在不同溫度載子遷移率..... 58
圖4-26 標準PMOS壓縮彎曲在不同溫度ION電流................59
圖4-27 SiGe S/D結構PMOS壓縮彎曲在不同溫度ION電流........59
圖4-28 標準PMOS伸張彎曲在低溫與室溫VG-NID 曲線...........60
圖4-29 SiGe S/D結構PMOS伸張彎曲在低溫與室溫VG-NID 曲線....60
圖4-30 標準PMOS伸張彎曲在不同溫度載子遷移率.............61
圖4-31 SiGe S/D結構PMOS伸張彎曲在不同溫度載子遷移率......61
圖4-32標準PMOS伸張彎曲在不同溫度ION電流........ .........62
圖4-33 SiGe S/D結構PMOS伸張彎曲在不同溫度ION電流........62
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