臺灣博碩士論文加值系統

在本論文的第一部份我們提出了一個適用於手持式數位電視(digital video broadcasting over handheld, DVB-H)系統之十位元、30 MHz取樣頻率的管線式類比數位轉換器。此類比數位轉換器是採用每級為1.5-bit之管線式架構。提出的設計在0.18 um CMOS製程下實現，差動輸入峰對峰範圍為2 V，而且佈局後模擬結果顯示當輸入為700 kHz的全擺幅正弦波時可以得到57.85 dBc的SFDR。在3.3 V的供應電壓下，最大消耗功率為37 mW，而晶片核心面積為0.27 mm2。
論文第二個部分中我們描述了一個使用典型CMOS 2P4M 0.35 um製程所製作之完全混合電壓共容輸出入單元設計。不同於傳統混合電壓共容輸出入單元，本設計可以傳送與接收的電壓訊號範圍為5/3.3/1.8 V。藉由在輸出級使用堆疊式PMOS與堆疊式NMOS以及利用電壓準位轉換器來提供堆疊式PMOS閘極適當之控制電壓，則閘極氧化層過度應力與熱載子降低等問題將可避免。並且使用閘極追蹤與浮動N型井電路來移除不預期之漏電流路徑。當負載電容為20 pF而且提供給I/O的供應電壓為5/3.3/1.8 V時，本設計的最快傳輸速度分別為103/120/84 Mbps。

The first topic of this thesis proposes a 10-bit, 30 Msample/s pipeline analog-to-digital converter (ADC) suitable for digital video broadcasting over handheld (DVB-H) systems. The ADC is based on the 1.5-bit-per-stage pipeline architecture. The proposed design is implement- ed by 0.18 um CMOS technology. The input range is 2 V peak-to-peak differential signals, and the post-layout simulation result shows that the spurious-free dynamic range (SFDR) is 57.85 dBc with a full-scale sinusoidal input at 700 KHz. The maximum power consumption is 37 mW given a 3.3 V power supply. The core area is 0.27 mm2.
The second topic is to propose a fully mixed-voltage-tolerant I/O cell implemented using typical CMOS 2P4M 0.35 um process. Unlike traditional mixed-voltage-tolerant I/O cell, the proposed design can transmit and receive the digital signals with voltage levels of 5/3.3/1.8 V. By using stacked PMOS and stacked NMOS at the output stage and a voltage level converter providing appropriate control voltages for the gates of the stacked PMOS, the gate-oxide overstress and hot-carrier degradation are avoided. Moreover, gate-tracking and floating N-well circuits are used to remove the undesirable leakage current paths. The maximum transmitting speed of the proposed I/O cell is 103/120/84 Mbps for the supply voltage of I/O cell at 5/3.3/1.8 V, respectively, given the load of 20 pF.

目錄
摘要 i
Abstract ii
目錄 iii
圖目錄 vi
表目錄 ix
第一章 概論 1
1.1 研究動機 1
1.2 文獻探討 2
1.2.1 適用於DVB-H接收系統之十位元30-MS/s管線
式類比數位轉換器 2
1.2.2 混合電壓共容輸出入單元設計 4
1.3 論文大綱 6
第二章 適用於DVB-H接收系統之十位元30-MS/s管線式類比
數位轉換器 7
2.1 簡介 7
2.2 電路架構與原理說明 8
2.2.1 S/H電路 9
2.2.2 1.5-bit ADC stage電路 12
2.2.3 動態比較器電路 15
2.2.4 錯誤更正電路 16
2.3 模擬結果 17
2.3.1 DNL/INL模擬結果 17
2.3.2 SFDR模擬結果 18
2.4 預計規格與比較 19
2.4.1 預計規格列表 19
2.4.2 效能比較 19
2.5 晶片佈局 20
2.5.1 佈局考量 20
2.5.2 佈局圖 21
2.6 晶片量測與討論 22
2.6.1 S/H電路量測 23
2.6.2 結論與討論 25
第三章 混合電壓共容輸出入單元設計 26
3.1 簡介 26
3.2 電路架構與原理說明 27
3.2.1 預先驅動電路 29
3.2.2 輸入級電路 29
3.2.3 輸出級電路 30
3.2.4 閘極追蹤電路 31
3.2.5 浮動N型井電路 31
3.2.6 電壓準位轉換器電路 32
3.2.7 靜態放電(Electrostatic Discharge, ESD)防護能
力 34
3.3 模擬結果 35
3.3.1 HSPICE模擬結果 35
3.4 預計規格與比較 38
3.4.1 預計規格列表 38
3.4.2 效能比較 38
3.5 晶片佈局 39
3.5.1 佈局考量 39
3.5.2 佈局圖 40
3.6 晶片量測與討論 41
3.6.1 Vg1電壓訊號量測 41
3.6.2 Vg2電壓訊號量測 43
3.6.3 VC2電壓訊號量測 45
3.6.4 輸出訊號量測 46
3.6.5 輸入級電路訊號量測 47
3.6.6 量測規格列表 48
3.6.7 結論與討論 49
第四章 結論與成果 51
參考文獻 53

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