臺灣博碩士論文加值系統

在半導體產業中，測試結構一向是被用以觀察新製程的參數變異範圍、建立製程邊界模型的重要方法之一。尤其當積體電路的製造技術演進到奈米銅製程以後，許多過去被視為較不重要的效應或不曾遭遇的問題，例如金屬內部互連、銅的化性、Low-k材質、CMP和次波長效應等挑戰不斷浮現。這些新的良率殺手更需要依賴各種特別設計的結構去達到製程的模擬與監控。目前業界在測試晶片的研發階段，傾向於利用電腦軟體自動化的優點，大量產生各樣驗證正確的測試結構以取代傳統專人手繪佈局圖、驗證、編寫文件這種費時耗力，成本高可靠度低的流程。
本篇論文重點為自動化產生金屬互連之測試結構的軟體，我們將針對過去李鴻志學長的Test-Gen軟體做改進。除了要把會嚴重造成製程失敗的化學機械研磨( Chemical Mechanical Polish，CMP )效應與光學微影這些知識加入新自動化軟體外，我們還引進細胞資料庫的概念，只要利用這些最小細胞作為結構的基底，再搭配模組化階層的架構，使用者就可以根據自我需求產生各式測試結構。除此之外，我們還提出一個全新的電容測試結構：四端點的comb測試結構。這個結構將有別於晶圓廠既有的二端點comb測試結構，它除了能夠做到結構本身電性或量測機台的驗證外，更重要的是，對於影響整體電容值的製程參數系統，我們在量測時，可以給予四端點不同的電壓組合，藉此觀察單一項參數的變動程度。這個新的結構設計已經內建在模組資料庫中，使用者可依需求去設定對應的參數，透過自動化程式快速的產生各種測試結構。總之，這個新的後端製程測試結構自動化產生軟體將大幅縮短測試晶片的開發流程，而且能隨製程變化做快速的調整，有助於加速後段製程邊界模型的開發。

In the semiconductor industry, test structures are the important method used to observe the parameters’ variation scope of new process, and establish process corner model. When the VLSI manufacturing technology develops from micro-Al to nanometer-Cu process, many problems which are secondary effects or never encounter before, such as the interconnect challenges, chemical property of copper, low-k material, CMP and the gap between sub-wavelength and silicon feature size……etc, now unceasingly occur. These new defects in particular need more special test structures in order to achieve the process simulation and monitor. Realizing the advantage of automation, industry nowadays tends to use computer software to massively generate all kinds of correct test structures. This efficient way will reduce conventional test chip development cycle, which is a person-months high cost but low reliability task.
In this paper, the automatic interconnect test structure generator is our key point. We’ll aim at Test-Gen by Hung-Chih Li to make the improvement. We not only add the knowledge of CMP effect, lithography constraint and the concept of cell library but provide the modulized architecture in the new automatic program so that users can generate each kind of test structure by their requirements. Besides, we propose a new 4-terminal comb test structure for capacitance measurement, which can decouple the process effects and verify the electrical properties of the test structure itself or the measurement machine. Users can instance the new structure in our build-in friendly template library. The overall flow from specification of different splits to final GDSII layout consumes little time, and can adjust fast along with the advance process. It’s helpful to accelerate the corner model development of the BEoL.

Abstract.............................................. i
中文摘要............................................ iii
圖片列表............................................. vi
表格列表........................................... viii
第１章 簡介........................................... 1
第２章 理論探討與前人文獻............................. 4
第１節 SIPPs Model................................ 4
第２節 測試結構................................... 6
第３節 CIF format................................. 6
第４節 應用軟體................................... 7
第５節 Test-Gen................................... 8
第１項 Test-Gen流程簡述....................... 8
第２項 Test-Gen提出的測試結構................ 11
第３項 Test-Gen的優缺點分析.................. 18
第３章 實做方法...................................... 22
第１節 使用環境.................................. 22
第２節 CMITG軟體架構............................. 23
第３節 CMITG軟體流程............................. 25
第４節 測試結構細胞分析.......................... 27
第１項 Comb cell (梳狀細胞).................. 27
第２項 Meander cell (蛇細胞)................. 29
第３項 Shield cell (盾狀細胞)................ 31
第４項 Taper cell (漸進細胞)................. 32
第５節 模具資料庫 (Template Library)............. 33
第１項 介電層厚度 ( Low-k-A thickness )...... 34
第２項 金屬線寬變動 ( CD bias ).............. 35
第３項 金屬層厚度 ( Metal thickness )........ 35
第４章 實驗設計...................................... 37
第５章 結論.......................................... 40
第６章 未來工作...................................... 41
參考文獻............................................. 44
附錄 A CMITG Syntax Description...................... 45
A-1 CMITG Syntax Notes.......................... 45
A-2 Conventions................................. 46
A-3 CMITG Statement Notes....................... 47
附錄 B CMITG Rules Description....................... 62

[1]. Hung-Chih Li, “Nanometer Interconnect Test Structure Generation Software for Comprehensive Process Variation Modeling for SoC Designs” June 2005.
[2]. Silicon Integration Initiative, Inc., “Standard Interconnect Performance Parameters (SIPPs),” version 1.06.01— 092200, Austin, TX, September 22, 2000.
[3]. Cadence Design Systems, Inc., "Design Data Translator’s Reference," version 5.1.41, San Jose, CA, June 2004.
[4]. INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS, "INTERCONNECT," version 2005.
[5]. Carver Mead et al, "Introduction to VLSI Systems," Addison-Wesley Publishers, 1980, Section 4.5.
[6]. K. Chang et al., “Accurate 3-D Capacitance Test and Characterization of Dummy Metal Fills to Achieve Design for Manufacturability,” 2005 CMP-MIC Conference, February 2005.
[7]. K. Chang et al., “Verify On-Chip Inductance Extraction with Silicon Measurement,” EE Times, November 2003.
[8]. Silicon Canvas, Inc., “Datasheet Laker T1 Test Chip Development Platform,” San Jose, CA.
[9]. J.R. Buchanan, "The GDSII Stream Format" June 2005.
[10]. Steven M. Rubin, “Computer Aids for VLSI Design” 1994