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研究生:邱創祺
研究生(外文):Chuang-Chi Chiou
論文名稱:使用統計學的方法分析電路的可測試性
論文名稱(外文):A Statistic-based Approach to Testability Analysis
指導教授:王俊堯王俊堯引用關係
指導教授(外文):Chun-Yao Wang
學位類別:碩士
校院名稱:國立清華大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:中文
論文頁數:31
中文關鍵詞:測試
外文關鍵詞:testing
相關次數:
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本論文提出一個利用統計的方法來計算出組合電路中每個節點的可測性。這個可測性分析的方法是將問題轉化為蒙地卡羅的模組來做模擬分析,透過定義模擬的條件後,蒙地卡羅的模擬能在結果達到我們事前所定義的信心水準以及誤差內停止。我們的實驗部分是使用一系列的ISCAS'85以及MCNC測資,和先前的研究相比,我們的方法更能有效的算出電路的可測性同時又有較高的準確度。
This paper presents a statistic-based approach for evaluating the testability of nodes in combinational circuits. This testability measurement is obtained via Monte Carlo simulation governed by the formulated Monte Carlo model. The Monte Carlo simulation is terminated when the predefined error with respect to the Monte Carlo model, under a specified confidence level, is achieved. We conduct the experiments on a set of ISCAS'85 and MCNC benchmarks. As compared with previous work, our approach more efficiently evaluates the testability with less error.
摘要 i
Abstract ii
致謝辭 iii
Contents iv
List of Figures vi
List of Tables vii
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Problem Formulation 2
1.3 Existing Approaches to Testability Analysis 2
1.4 Our Contributions 4
1.5 Overview 5
Chapter 2 Background 6
2.1 Monte Carlo Method 6
2.2 Parallel Pattern Simulation and Critical Path Tracing 8
Chapter 3 Our Approach 10
3.1 Random Pattern Generator (RPG) 10
3.2 Sampling Rules 11
3.3 Scoring 16
3.4 Error Estimation 17
3.5 Overall Flow 18
Chapter 4 Experimental Results and Analysis 20
4.1 Experimental Setup 20
4.2 Experimental Results of Runtime Comparison 21
4.3 Experimental Results of Error Distribution 23
4.4 Experimental Results of Detailed Information 25
4.5 Analysis 27
Chapter 5 Conclusions 28
Reference 29
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[2] V. D. Agrawal and S. C. Seth, “Probabilistic testability,” in Proc. Int. Conf. on Computer Design, pp.562-565, 1985.

[3] F. Brglez, “On testability of combinational networks,” in Proc.Int Symp. Circuits and Systems, pp.221-225, 1984.

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[8] R. K. Gaede, M. R. Mercer, and B. Underwood, “Calculation of greatest lower bounds obtainable by the cutting algorithm,” in Proc. Int. Test Conf., pp. 498-505, 1986.

[9] S. K. Jain and V. D. Agrawal, “Statistical fault analysis,” IEEE Design Test Comput., vol. 2, pp. 38-44, Feb. 1985.

[10] I. R. Miller, J. E. Freund and R. Johnson, “Probability and statistics for engineers,” Englewood Cliffs, NJ: Prentice Hall, 1990.

[11] K. P. Parker and E. J. McCluskey, “Probabilistic treatment of general combinational networks,” IEEE Trans. Comput., vol. C-24, pp. 668-670, 1975.

[12] J. Savir, G. S. Ditlow, and P. H. Bardell, “Random pattern testability,” IEEE Trans. Comput., vol. C-33, pp. 79-90, Jan. 1984.

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[14] E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. Sangiovanni-Vincentelli, “SIS: A system for sequential circuit synthesis,” Technical Report UCB/ERL M92/41, Electronics Research Lab, Univ. of California, Berkeley, CA 94720, May 1992.


[15] S. C. Seth, L. Pan, and V. D. Agrawal, “PREDICT: Probabilistic estimation of digital circuit testability,” in Proc. 15th Int. Fault-Tolerant Computer Symp., pp. 220-225, June 1985

[16] S. C. Seth and V. D. Agrawal, “An exact analysis for efficient computation of random-pattern testability in combinational circuits,” in Proc. 16th Int. Fault-Tolerant Computer Symp., pp. 318-323, 1986.

[17] O. Song and P. R. Menon, “Parallel pattern fault simulation based on stem faults in combinational circuits,” in Proc. Int. Test Conf., pp. 706-711, 1990.

[18] H. C. Tsai, K. T. Cheng, C. J. Lin, and S. Bhawmik, “A hybrid algorithm for test point selection for scan-based BIST,” in Proc. Design Automation Conf., pp. 478-483, 1997.

[19] D. T. Wang, “An algorithm for the generation of test sets for combinational logic network,” IEEE Trans. Comput., Vol. C-24, No. 7, pp. 742-746, July 1975.

[20] http://www.swox.com/gmp
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