臺灣博碩士論文加值系統

本論文主題為設計一個可供無線區域網路(WLAN)規格使用的四頻帶頻率合成器，這個頻率合成器包含一個切換電感式的壓控震盪器，可程式除頻器，相位頻率偵測器，電荷汞，和三線式控制介面。此頻率合成器目標的頻率輸出範圍是要涵蓋IEEE 802.11a/b/g規格所規範的四個頻帶，也就是ISM(2.4~2.4835GHz)頻帶，UNII-1(5.15~5.25GHz)，UNII-2(5.25~5.35GHz)，和UNII-3(5.725~5.825GHz)頻帶。此頻率合成器中使用的壓控震盪器採取了一種新型的電感切換方式。這種新型電感切換方式可以讓壓控震盪器切換兩段相差較大的頻率輸出範圍而依然保持低相位雜訊和低功率消耗。此論文還提出一個除數範圍為512~1023的多模數除頻器的設計，達到的最大的操作頻率為6GHz。整個頻率合成器經過模擬後利用TSMC提供的互補式金氧半(CMOS)0.18 製程實現。量測到的頻率可調範圍在低頻帶為1.94GHz到2.41GHz，而在高頻帶則為4.4GHz到5.16GHz。頻率合成器操作在低頻帶時的相位雜訊在偏離中心載波頻率1MHz為低於-114dBc/Hz。整個頻率合成器的下線晶片面積為1.083 x 1.083 ，消耗的功率為20 mW。

This thesis presents the design of a fully integrated quad-band frequency synthesizer, which includes a switched-inductor VCO, programmable frequency divider, phase-frequency detector, charge pump, and 3-wire interface. The target frequency range of the synthesizer covers the four frequency bands specified by IEEE 802.11a/b/g standards which are the ISM band, UNII-1, UNII-2, and UNII-3 band. The VCO adopts a novel inductor switching network that provides a large switched frequency range with low phase noise and low power consumption. A multi-modulus prescaler with division number 512~1023 is proposed to achieve maximum 6GHz operation frequency. The fully integrated frequency synthesizer is implemented in TSMC 0.18 CMOS process. The measured frequency tuning ranges in the lower and upper bands are from 1.94GHz to 2.41GHz and 4.4GHz to 5.16GHz respectively. The PLL phase noise in the lower band is less than -114 dBc/Hz at 1MHz offset frequency. The total chip area is 1.083 x 1.083 and the power consumption is 20mW.

1 Introduction
1.1 Background
1.2 Motivation
1.3 Thesis Organization
2 Architecture and Analysis of PLL
Frequency Synthesizer
2.1 Introduction
2.2 Phase-Locked Loop
2.2.1 Phase-Locked Loop Fundamentals
2.2.2 Linear Model Analysis
2.3 PLL Building Blocks
2.3.1 Phase-Frequency Detector
2.3.2 Charge Pump and Loop Filter
2.3.3 Voltage Controlled Oscillator
2.3.4 Frequency Divider
2.4 Frequency Synthesizer Design Specifications
2.4.1 Output Frequency Range and Resolution
2.4.2 Phase Noise
2.4.3 Locking Time
2.5 Phase Noise Analysis of PLL
2.5.1 Phase Noise of Reference Frequency
2.5.2 Phase Noise of VCO
2.5.3 Phase Noise of Other Building Blocks
2.6 Frequency Synthesizer Behavior Model
2.6.1 Behavior Model Setup
2.6.2 Simulation Results
3 Switched-Inductor Voltage Controlled Oscillator
3.1 Basics of Voltage Controlled Oscillator
3.1.1 Oscillation Theory
3.1.2 Oscillator Characteristics
3.1.3 Phase Noise Analysis of LC Tank Oscillator
3.2 Design of Switched-Inductor VCO
3.2.1 Passive Components
3.2.2 Analysis of a Switched-Inductor Resonator
3.2.3 Switched-Inductor VCO Core Circuit
3.2.4 Inductor Switching Network
3.2.5 Digital Varactor Array
3.2.6 Constant-Gm Bias Circuit
3.3 Simulation Results
3.4 Circuit Layout
3.5 EM Simulation of Inductor Switching
3.5.1 Analysis of New Inductor Switching Network
3.5.2 EM Simulation Results
4 A Quad-Band Frequency Synthesizer with
Switched-Inductor VCO
4.1 Frequency Synthesizer Architecture Overview
4.2 High Speed Programmable Frequency Divider
4.2.1 Frequency Divider in Synthesizer
4.2.2 Programmable Frequency Prescaler
4.2.3 Frequency Divider Architecture and Power Dissipation
4.2.4 Building Block Implementation
4.2.5 Simulation Results
4.2.6 Layout
4.3 Other Building Block Implementation
4.3.1 Phase-Frequency Detector
4.3.2 Programmable Charge Pump
4.3.3 3-Wire Interface
4.4 Simulation Summary
4.5 Circuit Layout
5 Measurement Results
5.1 Preparations for Measurement
5.2 Measurement Results
5.2.1 Measurement Results of VCO
5.2.2 Measurement Results of Frequency Divider
5.2.3 Measurement Results of Frequency Synthesizer
5.3 Measurement Discussion
6 Conclusion and Future Work
6.1 Conclusion
6.2 Future Work

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