臺灣博碩士論文加值系統

在這篇論文中，標準規格的研習，函數的模擬，架構設計和電路設計，以及應用於HomePlug AV(HPAV)的基頻通訊系統並且實現於場效式可程式閘陣列(FPGA)將被提出。

HPAV是電力線通訊系統的一個標準，在這篇論文中將提出一個遵守HPAV標準的基頻通訊系統。一個包含傳輸端、通道模型、接收端的基頻通訊實體電路層(PHY layer)將被模擬並實現。分離複頻調變(DMT)被使用在這個基頻通訊系統中，這種調變技術是一種為了有線通訊的正交分頻多工調變(OFDM)技術。根據HPAV標準，採用的一個非2次冪的3072點的快速傅利葉轉換(FFT)處理器架構，質因數演算法將被使用在實現這個快速傅利葉轉換(FFT)處理器架構。在HPAV標準裡，映射(mapping)是高階的(1024-QAM)，同步碼(preamble)的設計符合HPAV標準的要求並且提供接收端足夠的訊息。為了驗證被提出的設計，在[1]的通道模型被使用，這些通道效應包含了雜訊、干擾、多重路徑效應和取樣頻率漂移。

這個電路設計場效式可程式閘陣列(FPGA)中被實現並做驗證，信號產生器 (PG)被使用來製造輸入信號而邏輯分析儀(LA)是被使用來做輸出信號的分析。

In this thesis, standard specification study, functional simulation, architecture design and circuit design along with FPGA implementation of a baseband communication system for HomePlug AV (HPAV) applications is presented.

HPAV is a standard for the powerline communication system. A baseband communication system depending on HPAV standard is proposed in this thesis. A physical layer (PHY)of basedband communication system including transmitter, channel model, and receiver is simulated and implement. Discrete multitone modulation (DMT) is used in the baseband communication. This modulation is one kind of OFDM system for wire communications. According to HPAV standard, the 3072-point FFT processing architecture is adopt and it is not the power of two. The prime-factor algorithm (PFA) is used to implement the FFT processing architecture. The mapper is high order (1024-QAM) in HPAV standard. The structure of the preamble symbol matches the request of HPAV standard and supports enough information to receiver. In order to verify the proposed design, the channel model is used in [1]. The channel effect includes Noise, disturbances, multipath effect and, sample frequency offset(SFO).

The circuit design is implemented and verified by FPGA emulation. The pattern generator (PG) is used for input pattern generating and the logic analyzer (LA) is used
for output analysis.

1 Introduction 1
1.1 Overview of Powerline Communications
1.2 Motivation and Goal of the thesis
1.3 Organization of this thesis
2 Channel Characteristics of PowerLine
2.1 Noise and Disturbances
2.2 Channel Impedance
2.3 Signal Attenuation
2.4 Multipath Effect
3 Physical Layer Specification for HomePlug AV Systems
3.1 Basic Principle of DMT
3.2 HomePlug AV System
3.3 PHY Layer Feature of HPAV System
3.3.1 Turbo Code
3.3.2 IFFT and FFT
3.3.3 QAM
3.3.4 Bit-Loading
3.4 The Regulatory Environment
3.5 Channel Impairments
3.5.1 Attenuation
3.5.2 Multipath Effect
3.5.3 Time Variations
3.5.4 Noises
4 System Design
4.1 System Design Flow
4.2 Proposed System Parameter
4.2.1 Data Rate
4.3 Transmitter Block Diagram
4.3.1 Mapping Modulation
4.3.2 Gray code
4.3.3 3072-point IFFT Architecture
4.3.4 Preamble Symbol Generation
4.4 Channel Impairments
4.4.1 Multipath Effects
4.4.2 Additive White Gaussian Noise(AWGN)
4.4.3 Sample Frequency Offset (SFO)
4.5 Receiver Architecture
4.5.1 Packet Detection
4.5.2 Boundary Detection
4.5.3 Channel Estimation and FEQ
4.5.4 Phase Tracking
4.5.5 Phase Rotation
4.5.6 De-Mapping
4.6 Functional Simulation
4.7 Floating-Point Performance Simulation
4.8 Fixed-Point Model Simulation
5 Circuit Design and Implementation
5.1 Transmitter
5.1.1 Data modulator
5.2 Receiver
5.2.1 Packet Detection
5.2.2 Boundary Detection
5.2.3 FFT
5.2.4 Channel Estimation and FEQ
6 FPGA Emulation
6.1 FPGA Broad
6.2 Pattern Generator (PG)
6.3 Logic Analyzer (LA)
6.4 Measurement and Analysis
6.4.1 Functional Verification
6.4.2 Gate Count Analysis
7 Conclusions
7.1 Future Works
7.2 Conclusions

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