臺灣博碩士論文加值系統

在此篇論文中，從研讀標準規格開始、模擬功能性、定義系統架構、到設計電路與實作場效可程式邏輯閘陣列(FPGA)之後，提出了一個符合ECMA-368標準、全數位式同步且適用於高速超寬頻(UWB)傳輸的基頻收發機。
此基頻收發機的傳輸速率可達480Mb/s，並且可以符合ECMA-368標準所規範最高的資料傳輸生產量。為了達到如此高的資料傳輸生產量，此基頻收發機採用了平行四路資料處理的架構。它的前端取樣頻率為528MHz，因此，此基頻收發機的操作頻率操作在132MHz以上。
此一被提出的基頻收發機包含好幾個功能，分別是時間同步(Timing Synchronization)、頻率同步(Frequency Synchronization)、快速傅利葉轉換(FFT)、通道估測(Channel Estimation)、等化(Equalization)、相位追蹤(Phase Tracking)、以及解調變(De-Modulation)。大部份的功能都是選擇了適合的現有演算法來實作，然而，解調變提出了一個新的訊號處理演算法。這個演算法結合了最大可能性偵測機、雙載波調變(Dual-Carrier Modulation)的映像規則、以及一些設計者的假設在一起。除此之外，四種多重路徑模型(Multipath Model)以及正負百萬分之四十的漂移量的載波頻率漂移(Carrier Frequency Offset)和取樣頻率漂移(Sampling Frequency Offset)都被引用來模擬這個基頻收發機的效能。
Synopsis Design Compiler被應用在估測設計這個基頻收發機時的功率損耗、時脈、以及全部的閘總數(Gate Counts)。在此基頻收發機中的快速傅利葉轉換和反向快速傅利葉轉換的特點是單路徑延遲回授(Single-Delay Feekback)的架構以及平行四路的資料運作。藉由低功率消耗的設計技術，此雙核心快速傅利葉轉換及反向快速傅利葉轉換比起其它的設計消耗更少的功率且使用了較少的閘總數。
此外，此一被提出的基頻收發機的某些功能性區塊更使用場效可程式邏輯閘陣列來進行驗證。這個基頻收發機的硬體設計總共約消耗功率490mW以及使用了42萬個閘總數。

In this thesis, standard specification study, functional simulation, architecture definition, and circuit design along with FPGA implementation of the ECMA-368 [1] baseband
transceiver for high speed and ultra wideband transmission with full digital synchroniza-tion is presented.
A baseband transceiver with transmission rate up to 480 Mb/s is proposed and meets the highest transmission data throughput regulated in the standard ECMA-368. To reach such a high data throughput, a parallel-four signal processing architecture is adopted for this proposed baseband transceiver. The sampling frequency in the front-
end of the proposed baseband receiver is 528 MHz. Therefore, the operating frequency of this proposed baseband receiver operates above 132 MHz.
The proposed baseband transceiver includes several functional parts, timing synchronization, frequency synchronization, FFT, channel estimation, equalization, phase tracking and de-modulation. Most functional parts choose suitable existing algorithms to implement for the functionalities of themselves. However, a new signal processing algorithm is proposed for de-modulation. This algorithm combines a maximum likelihood detector, the dual carrier modulation (dcm) mapping rule, and some designer-made assumptions together. Four multipath models are quoted and ±40 ppm carrier frequency offset and sampling frequency offset are also added into the functional simulation of this
baseband transceiver.
Synopsis Design Compiler (DC) is applied to estimate the power consumption, the clock timing, and total gate counts for the hardware design of this baseband transceiver. The characteristic of the fast Fourier transform (FFT) and the inverse fast Fourier transform (IFFT) within this proposed baseband transceiver is the single-delay feedback architecture with parallel-four datapath. By some low power design techniques, the dual core FFT/IFFT consumes less power and less gate counts compared with others' design.
In addition, some functional blocks of the proposed baseband transceiver are even verified by FPGA. The total power consumption of this baseband transceiver is about
489 mW and the area is about 420 thousand gate counts.

1 Introduction
1.1 Overview of MB-OFDM UWB
1.2 Motivation of This Thesis
1.3 Organization of This Thesis
2 System Description
2.1 Rate-Dependent System Parameters
2.2 Physical Layer Specifications
2.2.1 Frame Format
2.2.2 Transmitter’s Architecture
2.2.3 Outer Transmitter
2.2.4 Inner Transmitter
3 System Design
3.1 Design Flow
3.2 Transmitter
3.3 Receiver
3.3.1 General Description
3.3.2 Packet Detector
3.3.3 Boundary Detector
3.3.4 Carrier Frequency Offset Estimator
3.3.5 Carrier Frequency Offset Compensator
3.3.6 Zero-Padding Remover
3.3.7 Fast Fourier Transform
3.3.8 Channel Estimator
3.3.9 Frequency-Domain Equalizer
3.3.10 Phase Tracker
3.3.11 Window Shift Controller
3.3.12 De-Mapper
4 Functional Simulation
4.1 Functional Simulation
4.1.1 Baseband Channel Impairments
4.1.2 Floating-Point Simulation
4.2 Word-Length Simulation
4.2.1 General Description
4.2.2 Transmitter’s Word-Length Determination
4.2.3 Receiver’s Word-Length Determination
4.2.4 Fixed-Point Simulation
5 Circuit Design
5.1 General Description
5.2 Transmitter Design
5.2.1 Preamble Generator
5.2.2 Dual-Carrier Modulation
5.2.3 Pilot Generator
5.2.4 Inverse Fast Fourier Transform
5.2.5 Summary
5.3 Timing Synchronization
5.3.1 Packet Detector
5.3.2 Boundary Detector
5.4 Frequency Synchronization
5.4.1 Carrier Frequency Offset Estimator
5.4.2 Carrier Frequency Offset Compensator
5.4.3 Zero-Padding Remover
5.5 Fast Fourier Transform
5.6 Channel Estimation
5.7 Phase Compensation
5.7.1 Phase Tracker
5.7.2 Window Shift Controller
5.8 Equalization
5.8.1 Frequency-Domain Equalizer
5.9 De-Modulation
5.9.1 De-Mapper
5.10 Quick Summary
5.10.1 FFT Comparisons
6 Implementation and Measurement
6.1 FPGA Board
6.1.1 FPGA Features
6.2 FPGA Emulation
6.2.1 Functional Verification
7 Future Works and Conclusions
7.1 Future Works
7.2 Conclusions

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