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研究生:洪佑仁
研究生(外文):Yu-Jen Hung
論文名稱:高效率多階層快閃記憶體之錯誤控制碼之解碼方法
論文名稱(外文):Efficient Decoding of Error Control Codes for Multilevel Flash Memories
指導教授:韓永祥
指導教授(外文):Yunghsiang S. Han
學位類別:碩士
校院名稱:國立臺北大學
系所名稱:通訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:英文
論文頁數:47
中文關鍵詞:硬體設計
外文關鍵詞:BCHcodeIC design
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  • 被引用被引用:0
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  • 下載下載:42
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近年來,新世代快閃記憶體因為半導體技術的進步,使得儲存單元越來越小,資料的干擾問題和維持問題卻變的越來越嚴重,也因此降低了記憶體的可靠度。為了增加記憶體的可靠性,錯誤更正碼被建議在記憶體的存取期間改正錯誤。已有一些應用在記憶體的錯誤更正碼之設計被提出。BCH 和 RS 碼是其中兩種最有效的代數碼被廣泛應用。在本篇論文中,將所有位元錯誤發生機率視為獨立發生的情況之下,考慮BCH(32767,32107,t=44)作編碼及解碼之設計。在我們的系統中,使用各種先進的架構。平行架構應用在syndrome區塊及Chien 搜尋區塊以減少時脈週期的數目。修改的歐幾裡得演算法被選擇用來解決關鍵方程式。修改的分組匹配算法被提出,用在降低Chien 搜尋架構以及編碼器裡,可以有效的降低乘法器的複雜度。最後以Xilinx FPGA確認及模擬編碼器/解碼器之架構。編碼器的最大頻率為288MHz而全部所需的gate count為16k。解碼器的最大頻率為76MHz而全部所需的gate count為242k。
In recent years, new-generation Flash memories have reduced cell size such that issues like disturbs and data retention become more and more critical. Consequently, the reliability of memories has decreased. In order to increase the reliability of memories, error control coding has been suggested to correct errors during memory reading. There are already some researches of the hardware design of error correcting codes in storage equipments. BCH and RS codes form the core of the most powerful known algebraic codes and are widely used .In this thesis, we focus on the encoder/decoder design of BCH(32767,32107,t=44) code under the condition that the error probability of all bits are independent. We propose various advanced architectures in our system. The parallel architecture is used to encoder block, syndrome block and Chien search block in order to reduce system's clock cycles. Modified Euclidean algorithm is chosen to solve the key equation. Modified group matching algorithm is proposed to minimize the complexity of the multipliers in encoder architecture and Chien search architecture. Finally, the encoder/decoder architecture is confirmed and simulated by Xilinx FPGA. The maximum frequency and total equivalent gate count for encoder are 268MHz and 16k. The maximum frequency and total equivalent gate count for the decoder are 76MHz and 242k.
1 Introduction 1
I Motivation 1
II Organization 3

2 Overview of Binary BCH codes 5
I BCH codes 5
II Encoder of BCH code 5
III Decoder of BCH code 6
III.1 Syndrome polynomial 7
III.2 Key equation 8
III.3 Chien search 12

3 Hardware design of BCH codes 13
I Specification 13
II BCH encoder architecture 14
III BCH decoder architecture 15
III.1 Syndrome computation 15
III.2 Solving key equation 21
III.3 Chien search 25

4 Simulation Results 37
I Encoder 39
II Decoder 39
II.1 Syndrome generator 39
II.2 Modified Euclidean algorithm 40
II.3 Chien search 41
III Results 43

5 Conclusions 45

Bibliography 46
[1] S. Lin and D. J. Costello, Error Control Coding, Prentice-Hall, Second Edition, 2004.
[2] D. Rossi, C. Metra, and B. Ricco, Fast and compact error correcting scheme for reliable multilevel Flash memories," in IEEE International Workshop on Memory Technology, Design and Testing(MTDT 2002), Italy, 2002.
[3] R. H. Morelos-Zaragoza, The Art of Error Correcting Coding, Wiley, 2002.
[4] H. M. Shao, T. K. Truong, L. J. Deutsch, J. H. Yuen, and I. S. Reed, A VLSI Design of a Pipeline Reed-Solomon Decoder," IEEE Trans. on Computers, vol. C-34, pp. 393-403, MAY 1985.
[5] T.-B. Pei and C. Zukowski, High-Speed Parallel CRC Circuits in VLSI," IEEE Trans. Commun., vol. 40, no. 4, pp. 653-657, April 1992.
[6] R. E. Blahut, Theory and Practice of Error Control Codes, Addison-Wesley Co., 1983.
[7] H.-J. Kwon and K. Lee, A New Division Algorithm Based on Lookahead of Partial-Remainder (LAPR) for High-Speed/Low-Power Coding Applications," IEEE Trans. on Circuits And Systems, vol. 46, no. 2, pp. 202-209, Feb. 1999.
[8] Y. Chen and K. K. Parhi, Small Area Parallel Chien Search Architectures for Long BCH Codes," IEEE Trans. on Very Large Scale Integration(VLSI) Systems, vol. 12, no. 5, pp. 545-549, May 2004.
[9] L.-L. Song, M.-L. Yu, and M. S. Shaffer, "10- and 40-Gb/s Forward Error Correction Devicesfor Optical Communications," IEEE Journal of Solid-State Circuits, vol. 37, no. 11, pp. 1565-1573, Nov. 2002.
[10] H. C. Chang, C. C. Lin, and C. Y. Lee, A low power Reed-Solomon decoder for STM-16 optical communications," in Asia-Pacific Conf. ASIC, Asia-Pacific, 2002.
[11] M. Potkonjak, M. B. Srivastava, and A. P. Chandrakasan, Multiple constant multiplications: Efficient and versatile framework and algorithms for exploring common subexpression elimination," IEEE Trans. Computer-Aided Design, vol. 15, pp. 155-165, Feb. 1996.
[12] C.-W. Chang, The IC design of a long BCH code," Master thesis, Graduate Institute of Communication Engineering, National Taiwan University, June, 2005.
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