臺灣博碩士論文加值系統

隨著製程微細化，閘極和絕緣層厚度都會呈比例縮小以減少晶片的面積。原本以多晶矽作為閘極而產生的閘極空乏區效應會逐漸明顯。使用金屬作為閘極不但能消除此效應，同時還有低阻抗等優點。但在使用金屬作為閘極的同時，必須克服金屬原有功函數所造成驅動電壓的限制，我們期望能找出一種調變金屬功函數的理想方法，以達成金屬閘極在未來最新半導體製程上的應用。在本論文中，我們利用介面處理的方式，成功讓金屬閘極的功函數有了-0.2eV到+0.3eV的調變。除此之外，在論文後半，我們為了多瞭解常見的金屬矽化物矽化鎳，試著去量測其介面一些性質如特徵接觸阻抗，最後還結合了四點探針量測與TLM量測成功去除探針接觸阻抗所造成的量測影響。

As CMOS devices are scaled down, gate electrode and insulate layer will also be scaled down in order to decrease the IC area. The poly depletion on poly silicon gate electrode will dominated total efficiency of the device, to use the metallic material as gate electrode can not only eliminate it but also provide lower gate electrode resistivity. The work function of the metals for NMOS and PMOS should be similar to that of n-Si and p-Si. However there is no clear conceptual understanding of how to design an interface with a given effective work function. In this thesis, we had find out some interfacial treatment that can shift metal gate work function form -0.2eV to +0.3eV. Beside, we had combine 4-point probe measurement principle on TLM pattern to measure NiSi ohmic contact resistivity.

第一章 介紹 1
1.1動機 1
第二章 實驗原理 4
2.1金屬的功函數 4
2.3歐姆接觸原理 10
2.4特徵接觸阻抗 13
2.5費米能階釘紮效應 15
第三章 實驗方法 17
3.1實驗流程 17
3.2表面清洗處理 19
3.3黃光微影製程 23
3.4電極製作以及圖形剝離 26
3.5快速熱退火 26
3.6電壓電容量測 28
3.7四點探針量測 33
3.8傳輸線模型理論 35
3.9光電子能譜儀 37
第四章 金屬閘極功函數實驗 40
4.1校正電容電壓量測儀器 40
4.2 蒸鍍氣壓對功函數的影響 43
4.3蒸鍍前塗布化學溶液於表面 46
4.4表面臭氧處理 48
4.5在金屬內加入氧化層 50
4.6誤差討論 53
4.7 結論與討論 55
第五章 特徵接觸阻抗量測實驗 56
5.1實驗目的 56
5.2實驗過程 59
5.3誤差討論 61
5.4 實驗方法改進 64
5.5結論 68
第六章 結語 69
6.1總結及未來展望 69
6.2貢獻 70
Reference 71

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