臺灣博碩士論文加值系統

頻率合成器在無線通訊系統中，扮演著一重要的角色，無論是發射機、傳輸機，都需要頻率合成器來產生本地震盪頻率。而且，發射機之實現，也可單獨藉由在鎖相迴路式頻率合成器之迴路內部調變來達成。因此，本論文將分為兩個主要的部份來介紹，且在進入主題之前，將會先介紹鎖相迴路的基本原理，包含了分析、模組化，以及提供了一個相位域(phase-domain)的數學模型來達到快速模擬，以及參數設計之驗證等功能。
在實現無線發射機的部份，利用了雙點調變的技巧來對鎖相迴路內部作調變，設計且實現了符合於IEEE 802.15.4規格中，應用於2.4-GHz ISM頻帶的無線發射機。量測之結果，在1.4伏特電源供應下消耗18毫瓦，且傳輸速率可達每秒兩百萬位元。
在本論文第二部份，介紹了三個可以增加線性度的電路技巧，包含了一具有動態平衡電流功能之電流幫浦、一受時脈控制之偏移電流技巧，以及一非平衡重置延遲式相位頻率偵測器。在文章中，同時也介紹了對於線性度之要求的原因，以及提供了線性度對系統效能影響之模擬，且模擬與量測結果大致上符合理論分析之結果。動態平衡電流式電流幫浦的使用時，可在較寬之迴路頻寬(1MHz)、參考頻率為20MHz的條件下，使用小面積的電流幫浦也可達到低於-60dBc的參考突波。至於時脈控制偏移電流技巧，可在對系統加入百分之十的偏移電流量之條件下，針對參考突波可改善約8dB。最後，在非平衡重置延遲式相位頻率偵測器的使用下，可在不增加額外電流源的情況下，同樣達到偏移操作區間(加入偏移電流之目的)之效果。

A frequency synthesizer plays an important role in wireless communication systems. Both transmitter and receiver need the synthesizer to generate local oscillation frequency. In addition, a transmitter can be implemented by utilizing the in-loop modulation of a phase-locked loop (PLL) based frequency synthesizer. This thesis is separated into two parts, transmitter implementation and synthesizer performance improvement, respectively. Before entering the two main sections, the fundamentals of a PLL were introduced first. The analysis, modeling, and a phase domain model are provided for quick simulation and parameters determination.
In the implementation of a transmitter, a scheme called “Two-Point Modulation” is employed for in-loop modulation of a fractional-N PLL. With this technique, a transmitter suitable for IEEE 802.15.4 standard in 2.4-GHz ISM-band application is designed, implemented, and measured. The measured power consumption is 18 mW under a 1.4-V supply voltage, and the achievable data rate is higher than 2 Mbps.
In the second part, three linearization techniques are introduced. A dynamic current-balancing charge pump, a gated-offset current scheme, and an unbalanced reset delay phase frequency detector (PFD) are introduced. The reasons of stringent linearity requirements are described, and the effects of nonlinearities on PLL performance are simulated. With theoretical analysis, the simulated and measured results agree with the hand-calculated results. With a 1-MHz wide loop bandwidth and a 20-MHz reference frequency, the new charge pump circuit achieves below -60 dBc reference spur with small-sized area. The gated-offset current obtains about 8-dB improvement with 10-% offset current applied to the PLL system. The new PFD realizes the shifting of operation region without additional current sources.

Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Overview 2
Chapter 2 Fundamentals of Fractional-N PLL 3
2.1 PLL Basics and Modeling 3
2.1.1 Voltage-Controlled Oscillators 4
2.1.2 Frequency Dividers 5
2.1.3 Phase Frequency Detector and Charge Pump 7
2.2 Fractional-N Frequency Synthesizer 7
2.3 Design Issues and Analysis of A PLL 10
2.4 Summary 12
Chapter 3 Two-Point Modulation Transmitter 13
3.1 Direct Modulation Schemes 13
3.2 Challenge for High Data Rate Modulation 17
3.3 Implementation of the Two-Point Modulation Transmitter 19
3.3.1 Proposed Two-Point Modulation Architecture 19
3.3.2 Building Blocks of This Transmitter 22
3.3.2.1 PFD and Charge Pump 22
3.3.2.2 Loop Filter 27
3.3.2.3 Voltage-Controlled Oscillator 31
3.3.2.4 Frequency Divider 34
3.3.2.5 Δ-Σ Modulator 36
3.4 Simulation 38
3.4.1 Behavior System Simulation 39
3.4.2 Transistor-Level System Simulation 42
3.5 Experimental Results 43
3.6 Conclusions 50
Chapter 4 Performance Improvement of Fractional-N PLLs 53
4.1 Introduction 53
4.2 Background and Issues 53
4.3 Linearization Techniques 55
4.3.1 Dynamic Current-Balancing Charge Pump 55
4.3.2 Gated-Offset Current Scheme 58
4.3.3 PFD/CP Linearization Technique 65
4.3.4 Fractional-N PLL Implementation 66
4.4 Simulation Results 69
4.5 Experimental Results 73
4.6 Conclusions 79
Chapter 5 Conclusions and Future Work 81
5.2 Conclusions 81
5.2 Future Work 83
Appendix A 85
Appendix B 87
Bibliography 89

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