臺灣博碩士論文加值系統

工作週期修正電路在許多高速電路應用上是非常實用的，如高速數位類比轉換器或類比數位轉換器或高速資料傳輸率的記憶體輸入及輸出介面[1-11]，在時脈控制上都是非常重要的。在雙倍資料傳輸率的同步SDRAM，更是同時使用了上升邊緣觸發及下降邊緣觸發去達到雙倍資料傳輸率。在這種應用中，使用50% 工作週期電路是非常關鍵重要的。新的工作週期修正電路與其他工作週期電路比起來有下列幾項特性，如可接受較寬範圍的輸入工作週期、操作頻率範圍較大、將輸入及輸出相位同步。
我們所提出的電路包含了一個時脈產生器及一個延遲偵測器。時脈產生器為輸入上升邊緣觸發及產生一個可藉由延遲偵測器將脈衝寬度調整為輸入週期的一半，另外，亦可以保存輸入訊號的資訊。由於輸入端爲上升邊緣觸發的DFF，所以輸入週期不會受到輸入週期的影響。本電路使用0.35-μm CMOS製程。我們使用單邊頻帶(single-sideband)的混波測試方式來增加量測輸出工作週期的精準度。此電路操作頻率為70 MHz ~ 500 MHz，操作在500 MHz時，可接受寬範圍的輸入工作週期為5% ~ 95%，輸出工作週期為50% ± 1.4%；操作在70 MHz時，可接受寬範圍的輸入工作週期為0.6% ~ 99.4%，輸出工作週期為50%。
在3.3伏特的提供電壓下，操作於70 MHz時，電流消耗為2 mA；操作於500 MHz時，電流消耗為7 mA。整體的晶片面積為1.1 mm*1.1 mm，其中亦包含了PAD、混波器及100 pF的電容，主要工作週期修正電路面積為0.5 mm*0.55 mm。

A 50% duty-cycle correction (DCC) circuit is reported in this thesis. The proposed DCC circuit consists of a clock generator and a delay detector. The clock generator is edge-triggered by the input and produces an output whose pulse width is adjusted to half of the signal period by the delay detector. Meanwhile, the input phase information is maintained. The proposed new DCC circuit has many features, including a wider acceptable duty-cycle range of the input clock, a larger operating frequency, synchronizing output phase with input phase. The circuit is implemented in a 0.35-μm CMOS process. To evaluate the output duty-cycle accuracy, a single-sideband mixing test method is adopted. This circuit operates from 70 MHz to 500 MHz, and accommodates duty cycles ranging from 5% to 95% at 500 MHz. The output signal is corrected to 50% ± 1.4%. Operated from a 3.3-V supply, the circuit dissipates 2 mA at 70 MHz and the circuit dissipates 7 mA at 500 MHz. This fully-integrated DCC chip area is 1.1 mm*1.1 mm, including pads, mixer, and an on-chip loop capacitor (100 pF), the core area is 0.5 mm*0.55 mm.

Acknowledgements…………………………………………………………… i
Chinese Abstract…………………………………………………………… v
Abstract………………………………………………………………………… vii
Contents………………………………………………………………………… ix
List of Figures………………………………………………………………… xi
List of Tables………………………………………………………………… xvii

1. Introduction 1
1.1 Background and Motivation………………………………………… 1
1.2 General Architectures of DCC………………………………………… 2
1.3 Thesis Overview……………………………………………………… 10

2. Introduction to Delay-Locked Loop 11
2.1 Delay-Locked Loop Basics………………………………………… 11
2.2 Simple Model and Analysis of the DLL ……………………………… 14
2.3 Behavior Simulation of the DLL……………………………………… 16

3. The Proposed Duty-Cycle Correction Architecture 19
3.1 Introduction of the Proposed Architecture…………………………… 19
3.2 Behavior Simulation of the Proposed DCC…………………………… 22
3.3 Building Block Designs……………………………………………… 25
3.3.1 Positive Edge-Triggered TSPC DFF…………………………… 25
3.3.2 Voltage-Controlled Delay Line………………………………… 26
3.3.3 Initialization Circuit and Pulse Generator…………………… 28
3.3.4 Phase Frequency Detector and Charge Pump………………… 29
3.5.5 Loop Filter and Stability……………………………………… 32
3.5.6 Auto Delay Selection Circuit………………………………… 32
3.6 Design Considerations………………………………………………… 34

4. Measurement Techniques 35
4.1 Conventional Time-Domain Measurement Technique…………… 35
4.2 Proposed Frequency-Domain Measurement Method and Theory…… 36
4.2.1 Principle of Single-Sideband Mixing………………………… 36
4.2.2 Architecture of Mixer and Divider…………………………… 38

5. Experimental Results 41
5.1 Test Setup and Equipments…………………………………………… 41
5.2 Printed Circuit Board Implementation and Assembly……………… 42
5.3 Measurement Results………………………………………………… 44
5.4 Performance Summary……………………………………………… 56

6. Conclusions 59

Bibliography……………………………………………………………………… 61
Publications……………………………………………………………………… 65

[1] Thomas H. Lee, Kevin S. Donnelly, John T. C. Ho, Jared Zerbe, Mark G. Johnson, and Tom Ishikawa, “A 2.5 V CMOS Delay-Locked Loop for an 18 Mbit, 500 Megabytes/s DRAM,” IEEE Journal of Solid-State Circuits, vol. 29, pp. 1491-1496, Dec. 1994.
[2] Yi-Ming Wang and Jinn-Shyan Wang, “An All-Digital 50% Duty-Cycle Corrector,” IEEE International Symposium on Circuits and Systems, vol. 2, pp. II-925-II-928, May, 2004.
[3] A. Waizman, “A Delay Line Loop for Frequency Synthesis of De-Skewed Clock,” IEEE International Solid-State Circuits Conference, pp. 298-299, Feb. 1994.
[4] C. Yoo, C. Jeong, and K. Kih, “Open-Loop Full-Digital Duty Cycle Correction Circuit,” IEE Electronics Letters, vol. 41, Issue 11, 26 May, 2005.
[5] Joonsuk Lee and Beomsup Kim, “A 250MHz Low Jitter Adaptive Bandwidth PLL,” IEEE International Solid-State Circuits Conference, pp. 346-348, Feb. 1999.
[6] Bruno W. Garlepp, Kevin S. Donnelly, Jun Kim, Pak S. Chau, Jared L. Zerbe, Charles Huang, Chanh V. Tran, Clemenz L. Portmann, Donald Stark, Yiu-Fai Chan, Thomas H. Lee, and Mark A. Horowitz, “A Portable Digital DLL for High-Speed CMOS Interface Circuits,” IEEE Journal of Solid-State Circuits, vol. 34, no. 5, pp. 632-644, May, 1999.
[7] Y.C. Jang, S.J. Bae and H.J. Park, “CMOS Digital Duty-Cycle Correction Circuit for Multi-Phase Clock,” IEE Electronics Letters, vol. 39, Issue 19, 18 Sep. 2003.
[8] Youngkwon Jo, Yong Shim, Soohwan Kim, and Suki Kim, “A Mixed-Structure Delay Locked-Loop with Wide Range and Fast Locking,” IEEE International Symposium on Circuits and Systems, pp. 1937-1940, May, 2006.
[9] Toru Ogawa and Kenji Taniguchi, “A 50% Duty-Cycle Correction Circuit for PLL Output,” IEEE International Symposium on Circuits and Systems, vol. 4, pp. IV-21 -IV-24, May, 2002.