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[1]Antoine Jalabert, Srinivasan Murali, Luca Benini, Giovanni De Micheli, “×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip,” DATE''04, Volume II, pp.20884, 2004. [2]XpipesCompiler: A tool for instantiating application specific Networks on Chip [3]L. Benini, G. De Micheli, “Networks on Chips: A New SoC Paradigm,” IEEE Computer, vol. 35, no. 1, pp. 70-78, Jan. 2002. [4]D. Bertozzi et al., “NoC synthesis flow for customized domain specific multiprocessor systems-on-chip,” IEEE Trans. Parallel Distrib. Syst.,vol. 16, no. 2, pp. 113–129, Feb. 2005. [5]D. Bertozzi, L. Benini, “Xpipes: A Network-on-Chip Architecture for Gigascale Systems-on-Chip,” IEEE Circuits and Systems Magazine, vol. 4, no. 2, pp.18-31, 2004. [6]Zhonghai Lu, Axel Jantsch, “Traffic Configuration for Evaluating Networks on Chips,” IWSOC, pp. 535-540, July. 2005. [7]P. Pande, C. Grecu, M. Jones, A. Ivanov, R. Saleh, “Evaluation of MP-SoC Interconnect Architectures: A Case Study,” International Workshop on System on Chip for Real-Time Applications, pp. 253-256. , 2004. [8]Jingcao Hu, Marculescu R., “Application-specific buffer space allocation for networks-on-chip router design,” ICCAD-2004, pp. 354 – 361, 7-11 Nov. 2004. [9]Dong Wu, Bashir M. AI-Hashimi, Marcus T. Schmitz, “Improving Routing Efficiency for Network-on-Chip through Contention-Aware Input Selection,” Interconnect for high-end SoC, pp. 36 - 41, 2006. [10]BONE, Basic On-Chip Network, http://ssl.kaist.ac.kr/ocn/. [11]W. J. Dally and B. Towles, “Route packets, not wires: On-chip interconnection networks,” DAC, pp. 684-689, USA, 2001. [12]William James Dally, Brian Towles, “Principles and Practices of Interconnection Networks,” Morgan Kaufmann, 2003. [13]S. Murali and G. De Micheli, “Bandwidth Constrained Mapping of Cores onto NoC Architectures,” in Proceedings of Design, Automation and Test in Europe Conference and Exhibition (DATE), vol. 2, pp. 896-901, Feb. 2004. [14]E. Nilsson, M. Millberg, J. Oberg, and A. Jantsch, “Load distribution with the proximity congestion awareness in a network on chip,” DATE, pp. 1126-1127, 2003. [15]Partha Pratim Pande, Grecu C., Jones M., Ivanov A., Saleh R., “Performance evaluation and design trade-offs for network-on-chip interconnect architectures,” IEEE Transactions on Computers, Volume 54, pp.1025 – 1040, Aug. 2005. [16]Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park, “A Gracefully Degrading and Energy-efficient Modular Router Architecture for On-Chip Networks,” Proceedings of the 33rd International Symposium on Computer Architecture, pp. 4 - 15 , June 2006. [17]Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo, “Low-power network-on-chip for high-performance SoC design,” IEEE Transactions on VLSI Systems, Volume 14, Issue 2, pp. 148 – 160, Feb. 2006. [18]Kangmin Lee, et al, “A 51mw 1.6GHz On-Chip Network for Low-Power Heterogeneous SoC Platform,” ISSCC Digest of Technical Papers, pp. 152-153, 2004. [19]Oqras U.Y., Marculescu R., ““It''s a Small World After All”: NoC Performance Optimization Via Long-Range Link Insertion,” IEEE Transactions on VLSI Systems , Volume: 14, Issue: 7, pp. 693- 706, July 2006. [20]E. Rijpkema, K. Goossens, A. Radulescu, J. Dielissen, J. Van Meerbergen, P. Wielage, and E. Waterlander, “Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip,” IEE Proceedings: Computers and Digital Techniques, vol. 150, pp. 294-302, 2003. [21]S. Murali and G. De Micheli, “Bandwidth-constrained mapping of cores onto NoC architectures,” Proc. DATE, pp. 896–903, Mar. 2004. [22]T. Ohira and R. Sawatari, “Phase transition in computer network traffic,” Phys. Rev. E, vol. 58, pp. 193–195, 1998. [23]M.Woolf, D. K. Arrowsmith, R. J. Mondragon-C, and J. M. Pitts, “Optimization and phase transitions in a chaotic model of data traffic,” Phys. Rev. E, vol. 66, p. 046106 , Nov. 2002. [24]J. Hu and R. Marculescu, “DyAD - Smart routing for networks-on-chip,” DAC, pp. 260-263, USA, 2004. [25]T. T. Ye, L. Benini, and G. De Micheli, “Packetization and routing analysis of on-chip multiprocessor networks,” Journal of Systems Architecture, vol. 50, pp. 81-104, 2004. [26]Jongman Kim, Dongkook Park, Theocharides T., Vijaykrishnan N., Das C.R., “A Low Latency Router Supporting Adaptivity for On-Chip Interconnects,” Design Automation Conference, pp. 559 - 564, 2005. [27]P. Guerrier, A. Greiner, “A Generic Architecture for On-Chip Packet-Switched Interconnections,” Proc. Design and Test in Europe (DATE), pp. 250-256, Mar. 2000. [28]P.P. Pande, C. Grecu, A. Ivanov, R. Saleh, “Design of a Switch for Network on Chip Applications,” Proc. Int’l Symp. Circuits and Systems (ISCAS), vol. 5, pp. 217-220, May 2003.
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