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研究生:林志政
研究生(外文):Chih-Cheng Lin
論文名稱:使用倍數延遲鎖定迴路技術之時脈產生器
論文名稱(外文):The Clock Generator using MDLL technique
指導教授:曹恆偉曹恆偉引用關係
指導教授(外文):Hen-Wai Tsao
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:中文
論文頁數:96
中文關鍵詞:延遲鎖定迴路循環式延遲脈衝產生法時脈產生器相位偵測器有效捕捉範圍
外文關鍵詞:Delay-Locked LoopCyclic Pulse GenerationClock Synthesizeracquisition range of PD
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傳統的倍數延遲鎖定迴路(Multiplying Delay-Locked Loop, MDLL)的鎖定行為,必須先利用一個外部重置訊號將全部延遲調整到最小延遲,再逐漸增加延遲來鎖定迴路,這是為了避免循環式延遲線所產生的全部延遲超過了相位偵測器的有效捕捉範圍,使延遲鎖定迴路的負迴授機制無法回復至其近似鎖定狀態,因此產生的時脈無法由低操作頻率轉換至高操作頻率,且輸出頻率範圍受到限制。
本論文提出應用於倍數延遲鎖定迴路時脈產生器的頻率偵測器,利用改良式頻率偵測器的選擇機制來解決上述提到的問題提出控制理論。並使用互補式金氧半電晶體0.35μm的製程以實做晶片且量測的方式來驗證想法。本設計可以產生37.5~444MHz的輸出時脈,不需額外的啟動控制電路即可將迴路鎖定在正確時脈頻率上,且可避免諧波鎖定等錯誤情況,因為本設計不需外部訊號來控制電路初始時的總延遲量,故可以相容於使用鎖相迴路時脈合成器作為內部時脈的系統。
接著針對頻率偵測器的邏輯電路再進行改良,提出一個新的頻率偵測器來鎖定迴路且改善缺點,簡單可行的電路架構更增加了實際上的應用性。
An external signal is necessary in the locking process of the traditional multiplying delay-locked loop. It is used to set total delay of the cyclic delay line in acquisition range of the phase detector, or the whole loop would be out of control. The output clock range of the clock synthesizer using cyclic pulse generation technique is limited by the acquisition range of the PD, and the clock synthesizer could not change its output clock frequency from low to high.
An approach to solve the above question by using a phase detector with frequency selection is proposed in this thesis. The control algorithm of the approach is introduced and implemented in CMOS 0.35μm process to verify it. This circuit design can synthesize output clock frequency from 37.5MHz to 444MHz without extra start-up circuit and the external signal to control the initial total delay. This work overcomes the drawbacks of the clock synthesizer using MDLL technique, and is incorporated into the systems which use traditional PLL as clock synthesizer.
More effects are done to simplify the circuit design and control algorithm in the rest part of the thesis, and the algorithm is verified by software tool, SIMULINK.
論文審定書(中文) i
論文審定書(英文) iii
誌謝 v
中文摘要 vii
Abstract ix
目錄 xi
圖片目錄 xiii
表格目錄 xvi
第一章 緒論 1
1.1 動機 1
1.2 論文架構 2
第二章 延遲鎖定迴路 3
2.1 基礎理論與架構 3
2.1.1 延遲鎖定迴路的特性 3
2.1.2 迴路特性分析 6
2.1.3 第一類型延遲鎖定迴路抖動轉換特性 9
2.2 延遲鎖定迴路的組成方塊 11
2.2.1 壓控延遲線 11
2.2.2 相位偵測器 14
2.2.3 電荷幫浦 18
2.3 延遲鎖定迴路的應用 22
2.3.1 頻率合成器 22
2.3.2 時脈誤差修正電路 24
2.3.3 資料鏈結 25
第三章 以倍數延遲鎖定迴路為基礎之時脈產生器 27
3.1 倍數延遲鎖定迴路 28
3.2 相位偵測器的擷取範圍問題 31
3.2.1 傳統延遲鎖定迴路的諧波鎖定問題 31
3.2.2 循環式延遲脈衝產生法的鎖定範圍 32
3.2.3 倍數延遲鎖定迴路操作上的限制 35
3.2.4 解決倍數延遲鎖定迴路之相位偵測器擷取範圍限制的方法 36
3.3 電路架構與組成元件 38
3.3.1 壓控延遲線 40
3.3.2 頻率/相位偵測器 46

3.4 晶片量測的環境與結果 56
3.4.1 晶片量測環境 56
3.4.2 量測結果 61
3.5 結論 68
第四章 改良式頻率/相位偵測器與電荷幫浦 71
4.1 控制原理 72
4.2 頻率/相位偵測器架構與電荷幫浦 73
4.2.1 任意除數計數器 74
4.2.2 改良式選擇器電路 75
4.2.3 鎖定判斷器 76
4.2.4 相位偵測器 77
4.2.5 電荷幫浦 80
4.2.6 特殊起始狀態 82
4.3 模擬設定與結果 84
4.3.1 由過大延遲鎖定 85
4.3.2 由過小延遲鎖定 87
4.4 結論 90
第五章 總結與展望 91
5.1 總結 91
5.2 展望 92
參考文獻 93
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