臺灣博碩士論文加值系統

本研究將研製一套針對音頻類比至數位轉換器的三角積分調變器。研究目標將放在利用三角積分調變器，改善類比訊號轉換至數位訊號時容易產生的高量化雜訊，提升訊號對雜訊比(SNR)。
利用超取樣技巧的三角積分調變器，被廣泛地利用在積體電路系統中數位與類比信號的介面。這種方法相對來說，是對電路元件的瑕疵比較不敏感的，尤其在實現高解析度的類比數位轉換器中，超取樣的三角積分架構是比較節省能量的作法，因為比起一般的超取樣轉換器，它減少了類比電路的數量以及複雜度。更進一步的說，三角積分調變器中大多數的能量損耗以及性能的要求，都是在轉換器的輸入級。
此論文研究的重點，將放在使用比一般三角積分調變器更高的超取樣率 (128倍)，並增加音頻信號的頻寬達到25kHz，且使用「多級」(Multi-Stage)的架構增加信號輸入的最大位準，以達到更高的解析度，在如此高的超取樣率時，運算放大器的特性，以及電路元件的不匹配性及非理想效應，將有更嚴苛的要求，這是今日實現高階音響的重大挑戰。
此調變器的晶片實現是使用台積電0.35μm 2P4M的製程，晶片面積為1.2 x 1.2 mm2，在3.3V的供應電壓下，功率消耗為13mW。模擬中，在25kHz的基頻內，調變器的SNDR最大值可達到96.12dB，在佈局後模擬時，SNDR最大值可達到89dB。實驗結果顯示，此晶片在25kHz的基頻內，SNR的最大值為70dB，此時SNDR為60dB。其中造成落差的原因，應該是在晶片佈局時的瑕疵所引起，使得類比訊號受到數位訊號的雜訊所干擾。

This research investigates a sigma-delta modulator for audio analog-to- digital converter. The goal of this research is to improve the high quantization noise and enhance the signal-to-noise ratio (SNR) when converting analog signal to digital in use of sigma-delta modulator.
Oversampling techniques based on Σ-Δ modulation are wildly used to implement the interfaces between analog and digital signals in VLSI systems. This approach is relatively insensitive to imperfections in circuit components. In particular, oversampling architectures are potentially power-efficient means of implementing high resolution A/D converters because they reduce the number and complexity of the analog components in comparison with Nyquist-rate converters. Furthermore, they allow the performance requirements, and thus most of the power dissipation, to be concentrated in the input stage of a converter.
In this thesis, we pay attention on using higher oversampling rate (128) than general Σ-Δ modulator, increasing the based-band width of audio signal to 25 kHz, and utilizing the architecture of Multi-Stage Sigma-Delta modulator to increase the swing of input signals, in order to achieve higher resolution. The specification of the operational amplifier, the mismatch and imperfection of circuit component will face the severer requirement with such oversampling rate. It is really a great challenge when implementing high-quality audio nowadays.
This Multi-Stage Sigma-Delta Modulator is fabricated in TSMC 0.35μm Mixed-Signal 2P4M Polycide process. The area of this chip is 1.2 x 1.2 mm2 and power dissipation is 13mW under 3.3V supply voltage. In the Pre-layout simulation, the peak SNDR in the basband (25 kHz) can achieve 96.12dB; in the Post-layout simulation, the peak SNDR can be 89dB. Experimental result shows that the peak SNR is 70dB within the baseband of 25 kHz (SNDR is 60dB), which might be caused by the layout imperfection, making the analog circuit be disturbed by the noise from digital circuit.

Chapter 1. Introduction.................................1
1.1 Organization.....................................2
Chapter 2. Fundamentals.................................5
2.1 Analog-to-Digital Converters.....................5
2.1.1 Quantizer characteristics..................7
2.2 Oversampling A/D Converters......................11
2.2.1 Feedback Modulator.........................12
Chapter 3. Architecture of Sigma-Delta Modulator........15
3.1 First-Order Noise Shaping........................15
3.1.1 1st-order Modulator Topology...............15
3.1.2 Circuit impl. of 1st-order Σ-Δ modulator...17
3.1.3 Mod. Noise in 1st-order Σ-Δ Modulators.....19
3.2 Second-Order Noise Shaping.......................22
3.2.1 Mod. Noise in 2nd-order Σ-Δ Modulators.....22
3.2.2 2nd-order Modulator Topology...............24
3.2.3 Circuit impl. of 2nd-order Σ-Δ modulator...26
3.3 Higher-Order Noise Shaping.............26
3.3.1 Higher-order Single-stage Modulators.......26
3.3.2 Cascaded Sigma-Delta Modulators............28
Chapter 4. System Block and Behavior Simulation.........33
4.1 Modulator Architecture...........................33
4.2 Signal Scaling...................................35
4.3 Architecture Behavior Simulation.................37
4.4 Operational Amplifier Model......................40
Chapter 5. Circuit Design and Implementation............47
5.1 Circuit Design...................................48
5.1.1 Clock Generator............................48
5.1.2 Integrators................................49
5.1.3 Amplifiers used in the integrators.........53
5.1.4 Bias Circuit for Amplifiers................55
5.1.5 Quantizers behind two stages (1-bit ADC)...57
5.2 Simulation Result................................58
5.2.1 Clock Generator............................58
5.2.2 Amplifier..................................59
5.2.3 Bias Circuit...............................62
5.2.4 Quantizer (1-bit ADC)......................63
5.2.5 The Output Spectrum of The Σ-Δ Modulator...64
5.3 Experimental Result..............................65
5.3.1 Chip Implementation........................66
5.3.2 Layout Consideration.......................66
5.3.3 Simulation Result..........................67
5.3.4 Measurement Environment....................68
5.3.5 Measurement Result.........................71
Chapter 6. Conclusion ..................................75
6.1 Conclusion.......................................75
6.2 Recommendation...................................75
Reference................................................77

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