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研究生:李明華
研究生(外文):Ming-Hwa Lee
論文名稱:具寬線性範圍頻率偵測器之低抖動資料時脈回復電路
論文名稱(外文):A Low-Jitter Clock and Data Recovery Circuit with Wide-Linear-Range Frequency Detector
指導教授:李泰成
指導教授(外文):Tai-Cheng Lee
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:英文
論文頁數:61
中文關鍵詞:資料時脈回復電路相位偵測器
外文關鍵詞:Clock and Data RecoveryPhase Detector
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近年來的序列通訊系統傳送速度已高達每秒十億位元等級,因此大量的頻寬需求使的傳輸材料漸漸從傳統的銅轉變為光纖。由於低成本的考量,10GBASE乙太網路無論是在LANs 或是WANs皆伴演著重要的角色。而在通訊系統之接收端,資料與時脈回復電路被用來產生與接收資料同步之時脈並且去除輸入隨機資料的抖動。傳統上如此高速之電路通常是以 GaAs MESFET或 Si bipolar製程來實現,然而近年來CMOS 相關製程被認為更加適合用來實現這些高速電路,因為它的低成本,低功率消耗跟高度的整合能力。

本論文提出一個應用於10GBASE-LX4 乙太網路之31.25 億位元資料時脈回復電路設計。此電路採用一個低抖動哈吉型相位偵測器來降低輸出時脈之抖動跟一個寬線性範圍之頻率偵測器來縮短系統的頻率鎖定時間。由於資料時脈回復電路之頻寬通常被規格限制的很小,同時限制了資料時脈回復電路的鎖定範圍。如果沒有頻率取得迴路,資料時脈回復電路將會需要額外的外給參考時脈。由於較佳的製程,電壓跟溫度變異容忍能力,數位相關器的技術被大量使用在資料時脈回復電路的頻率取得迴路上。而本次的設計提出一個改良式的頻率偵測器來增加頻率迴路的線性操作區間並縮短頻率鎖定所需之時間。除此之外,我們也提出一個低抖動的哈吉型相位偵測器來減低輸出時脈的抖動而不需要改變到迴路的頻寬。本晶片是以0.18-μm 1P6M CMOS製程實現,而它的面積為0.61 毫米 × 0.61 毫米。本次提出的資料時脈回復電路量測結果,時脈抖動的峰對峰值為70 ps而其方均根值為 8.3 ps。輸入資料為231-1 PRBS時,位元錯誤率的量測結果小於10-12。而供給電壓為一點八伏特時,電路消耗的功率為61毫瓦。
In recent years, the speed of serial communication has been increased to multi-gigabits per second. The large demand of bandwidth converts the transmission medium from copper wire to fiber gradually. For both local area networks (LANs) and wide area networks (WANs), 10GBASE Ethernet plays an important role because of the low cost. In the receiver side, clock and data recovery (CDR) circuits can be employed to generate the clocks synchronized with received data and remove the jitter of input random data. Traditionally, GaAs MESFET or Si bipolar technology is usually used for implementing such high speed circuits. However, CMOS technologies are now considered in these high-speed circuits because of the low cost, low power dissipation, and highly integrated capability.

Designed for the applications of 10GBASE-LX4 Ethernet, a 3.125-Gb/s CDR is proposed to lower the output clock jitter and decrease the frequency acquisition time by employing a low-jitter Hodge phase detector and a wide-linear-range frequency detector. Due to the requirement of the small loop bandwidth of CDR, pull-in range is limited and CDR without frequency acquisition loops might need additional reference clocks. Digital quadricorrelator techniques are widely used for frequency acquisition loops because of the tolerance to process, voltage, and temperature variations. In this work, a modified frequency detector is proposed to widen linear range, which can decrease the frequency acquisition time. Besides, a low-jitter Hogge phase detector is also proposed to minimize output clock jitter with no need of loop bandwidth change. This chip is fabricated in a 0.18-μm 1P6M CMOS technology and occupies a chip area of 0.61 mm × 0.61 mm. The output jitter of this proposed CDR is measured 70 ps (peak-to-peak) and 8.3 ps (rms), and the measured bit-error rate (BER) is less than 10-12 for 231-1 PRBS. The power dissipation of core circuit is 61 mW from a single 1.8-V power supply.
Table of Contents I
List of Figures III
List of Tables VII


Chapter 1 Introduction 1

1.1 Motivation and Research Goals 1
1.2 Thesis Overview 2


Chapter 2 Basic Concepts and 10GBASE-LX4 System 3

2.1 Basic Concepts 3
2.1.1 Properties of Random Binary Data 3
2.1.2 Eye Diagram 4
2.2 Fiber Optic Transceiver 6
2.2.1 Semiconductor Technologies for Optical Network 6
2.2.2 Transmitter (TX) Building Block 6
2.2.3 Receivers (RX) Building Block 7
2.3 10GBASE-LX4 System Specifications 8
2.3.1 Jitter transfer 8
2.3.2 Jitter tolerance 8
2.3.3 Jitter generation 9


Chapter 3 System Architecture of Clock and Data Recovery (CDR) 11

3.1 Introduction to Clock and Data Recovery 11
3.1.1 Phase Detector of Random Data 11
3.1.2 Frequency Detector of Random Data 16
3.1.3 CDR Architectures 20
3.2 Jitter Performance of CDR 22

3.2.1 Jitter transfer 22
3.2.2 Jitter tolerance 23
3.2.3 Loop filter parameter design 25
3.3 Architecture of the Proposed CDR 27
3.3.1 Low-jitter Hogge Phase Detector 27
3.3.2 Wide Linear Range Frequency Detector 30
3.4 Behavioral Simulations 35
3.4.1 Second order Loop filter 35
3.4.2 Close-loop simulation 36


Chapter 4 Implementation of the Proposed Clock and Data Recovery with Wide Linear Range FD 39

4.1 Phase Detector 39
4.1.1 Latch 39
4.1.2 XOR and CP 41
4.1.3 Simulation result 42
4.2 Frequency Detector 44
4.3 Voltage Control Oscillator 46
4.4 Close-loop simulation result 48


Chapter 5 Experimental Results of the Clock and Data Recovery 51

5.1 Test Setup 51
5.2 Experimental Results 52


Chapter 6 Conclusions 57

6.1 Conclusions 57









List of Figures



Chapter 1


Chapter 2

Fig. 2.1 NRZ data and RZ data. 3
Fig. 2.2 Spectrum of NRZ random data. 4
Fig. 2.3 (a) Effect of low-pass filtering, and
(b) effect of high-pass filtering on random data. 5
Fig. 2.4 Eye mask for 10GBASE-LX4. 5
Fig. 2.5 The building block of transmitter. 7
Fig. 2.6 The building block of receiver. 7
Fig. 2.7 The jitter transfer mask of 10GBASE-LX4 system. 8
Fig. 2.8 The jitter tolerance mask of 10GBASE-LX4 system. 9


Chapter 3

Fig. 3.1 Architecture of the clock and data recovery. 11
Fig. 3.2 Hogge PD and its waveform. 12
Fig. 3.3 The triangular pulse on the control line. 13
Fig. 3.4 Three-sampling points (a) when the clock is early,
(b) when the clock is late. 13
Fig. 3.5 Alexander PD and its waveform. 14
Fig. 3.6 Characteristics of (a) linear PD and (b) binary PD. 15
Fig. 3.7 Architecture of the binary FD. 17
Fig. 3.8 Waveforms of (a) clock is faster and (b) clock is slower. 18
Fig. 3.9 (a) The sampling circuit of linear FD and
(b) the decision circuit of linear FD. 19
Fig. 3.10 (a) Dual loop CDR architecture and
(b) which with two loop filter. 21
Fig. 3.11 CDR architecture with external reference clock. 21
Fig. 3.12 Jitter transfer function. 22
Fig. 3.13 Jitter tolerance of a CDR. 24

Fig. 3.14 Second order loop filter. 25
Fig. 3.15 Architecture of 3.125-Gb/s CDR with modified PD and FD. 27
Fig. 3.16 Triangular pulses on the control line of Hogge PD. 28
Fig. 3.17 Modified Hogge PD [19]. 28
Fig. 3.18 Low-jitter Hogge PD in this work. 29
Fig. 3.19 Comparisons between the modified PD and the conventional PD. 30
Fig. 3.20 State representation. 31
Fig. 3.21 Random data property which brings the loss of state detections. 31
Fig. 3.22 Limited linear range of conventional FD. 32
Fig. 3.23 Comparison between modified FD and conventional FD. 34
Fig. 3.24 Frequency locking process of CDR using (a) conventional FD and
(b) modified FD. 34
Fig. 3.25 (a) Bode plot of the loop filter and
(b) the 0.097 dB jitter peaking. 36
Fig. 3.26 Close-loop simulation of locking process by MATLAB. 37


Chapter 4

Fig. 4.1 Circuit of the TSPC latch. 39
Fig. 4.2 D-latch circuit by CML. 40
Fig. 4.3 The circuit of XOR gate by CML. 41
Fig. 4.4 Charge pump circuit. 42
Fig. 4.5 Architecture of the modified PD. 42
Fig. 4.6 (a) Low-jitter Hogge PD with dummy delay stage,
(b) realization of the delay stage. 43
Fig. 4.7 Transfer curve of the PD by HSPICE. 44
Fig. 4.8 (a) Architecture of the modified FD, (b) Logic 1, (c) Logic 2, and
(d) Logic 3. 45
Fig. 4.9 Transfer curve of modified FD by HSPICE. 46
Fig. 4.10 Circuit of the VCO stage. 46
Fig. 4.11 Post-layout simulation result of VCO tuning range by HSPICE. 47
Fig. 4.12 Layout of the proposed 3.125-Gb/s CDR. 48
Fig. 4.13 Eyediagram of the retimed data. (post-layout simulation) 49
Fig. 4.14 Eyediagram of the recovered clock with (a) the conventional PD
(b) the modified PD. 50


Chapter 5


Fig. 5.1 Measurement environment. 51
Fig. 5.2 Photograph of the PCB. 52
Fig. 5.3 Photograph of the die. 52
Fig. 5.4 Measured tuning range of VCO. 53
Fig. 5.5 Eyediagram of the (a) retimed data and
(b) recovered clock for 27 – 1 PRBS. 54
Fig. 5.6 (a) Jitter histogram and
(b) frequency spectrum of the recovered clock. 54
Fig. 5.7 Measured BER by a 27 – 1 PRBS data. 54
Fig. 5.8 Eyediagram of the retimed data for 231 - 1 PRBS. 55
Fig. 5.9 Measured BER by a 231 – 1 PRBS data. 55


Chapter 6





































































List of Tables



Chapter 1


Chapter 2


Chapter 3

Table 3.1 A brief summation of comparisons between Hogge and
Alexander PD. 16
Table 3.2 The truth table of linear FD. 19
Table 3.3 Summary table of the modified PD. 30
Table 3.4 The truth table of conventional linear FD. 31
Table 3.5 The truth table of wide linear range FD. 32
Table 3.6 Parameters of the second order loop filter. 36


Chapter 4

Table 4.1 Parameters of this 3.125-Gb/s CDR. 49


Chapter 5

Table 5.1 Summary of measured VCO. 53
Table 5.2 Performance summary. 56
Table 5.3 Performance comparison. 56
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[14]K. Kishine, K. Ishii and H. Ichino, “Loop-Parameter Optimization of a PLL for a Low-Jitter 2.5-Gb/s One-Chip Optical Receiver IC With 1:8 DEMUX,” IEEE Journal of Solid-State Circuits vol. 37, pp. 38-50, Jan. 2002.

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