臺灣博碩士論文加值系統

本論文敘述使用先進的製程去實現類比電路數位化，來解決時脈的位移和工作週期的控制。由於類比電路數位化可以達到相當於類比電路的效能，而且全數位的設計具有高攜帶性以及在它可以輕易轉移到不同的製程上。它高整合性、低消耗功率和低抖動的特性也很容易整合在單一系統之中。在雙倍取樣的系統中，例如靜態記憶體和類比到數位轉換器，具有50% 工作週期的訊號是非常重要。因此，我們需要工作週期校正器使得時脈的校正工作週期自動校正到50%。

這本論文中提出一個全數位的寬度可控制迴路並可控制工作週期，輸出的時脈不但可以產生50%的工作週期，還可以調整工作週期30%~70%在每10%一個單位。一個時脈寬度偵測電路是使用連續式的時間轉化成數位電路來偵測輸入的工作週期。接著，我們提出把全數位的寬度可控制迴路放置於全數位延遲鎖相迴路中，所以得到輸出時脈同步於輸入時脈，同時得到可控制的工作週期。這兩個實驗晶片都是使用0.35um CMOS製程。

接著，我們發展全數位工作週期校正器的電路。第一測試晶片產生50%工作週期和同步於輸入時脈，可接受的工作週期和頻率範圍分別為40% 到60% 和 800 百萬赫茲到1200百萬赫茲。第二測試晶片有設計一個週期偵測器來偵測輸入時脈有週期變化時，能可自動產生50%工作週期。可接受輸入時脈的工作週期為10% 到90%和頻率範圍1億赫茲到1.6億赫茲。這全數位工作週期校正器的電路都是使用0.18um CMOS製程。

This thesis describes digital implemented the analog circuit with advanced standard sub-micro CMOS technology to solves of clock skew and duty cycle. The digital implemented IC can achieve a fine performance compare to the analog. It has high portability and scalability across different technology process. Its high integrity, low power, and low jitter performance can be easily incorporated into a single chip and successful realization of the system-on-a-chip (SOC). A clock with 50% duty cycle is extremely important in many double-rate systems such as DDR-SDRAMs and analog-to-digital converters. Therefore duty-cycle corrector (DCC) is needed to correct duty cycle as 50%.

This dissertation provides an all-digital pulsewidth control loop (PWCL) with adjustable duty cycle. The output clock is not only achieved 50% duty cycle, but can adjust from 30%~70% in steps of 10%. A pulsewidth detector using the sequential time-to-digital conversion is employed to detect the duty cycle of input clock. Then, we proposed the PWCL is embedded with an all-digital delay-locked loop. Therefore, the output of clock can synchronize with input clock and also with variable duty cycle. Both experimental chips have been fabricated in a 0.35um CMOS process. The operation frequency range is from 400 MHz to 600 MHz.

Next, we develop all-digital duty cycle corrector circuit; the first test chip generates the 50% duty cycle and synchronizes with input clock. The measurement results shows the proposed circuit operates with input frequency range with 0.8~1.2GHz and input 40%~60% duty cycle. The second test chip, a period monitor is used to track the period of input to keep 50% duty cycle, when the period of input clock is changed. The proposed circuit works for the input duty cycle of 10%~90% and the measured operation frequency range is from 1 GHz to 1.6 GHz. The all-digital duty cycle corrector circuits have been verified on silicon using 0.18um CMOS technology.

Abstract ……………………………………………...…… I
Contents ………………………………………………...… V
List of Figures……………………………………...…… IX
List of Tables ………………………………...…… XV

1. INTRODUCTION 1
1.1 Motivation…….…………………….. 1
1.2 Thesis Overview……………………... 2

2. The BASICS 5
2.1 Analog Delay-LockedLoop…….... 5
2.2 Digital Delay-Locked Loop……………. 8
2.3 Duty Cycle Correction Circuits……… 12
2.3.1 Open-Loop Type……………. 12
2.3.2 Closed-Loop Type…………… 13
2.4 Pulsewidth Control Loop………………. 15

3. ALL-DIGITAL PULSEWIDTH CONTROL LOOP WITH ADJUSTABLE DUTY CYCLE 19
3.1 Introduction……..…………………….. 20
3.2 Circuit Description………………….. 20
3.2.1 Pulse Generator and driver… 22
3.2.2 Delay line……………………. 22
3.2.3 Delay generator……………… 23
3.2.4 Pulsewidth Detector………… 24
3.2.5 Duty Cycle Correction Circuit 26
3.3 Performance Analysis…........... 27
3.4 Simulation Results………………… 29
3.5 Experimental Results…………….... 33
3.6 Summary…………...……………... 38


4. ALL-DIGITAL CLOCK DESKEW BFFER WITH VARIABLE DUTY CYCLES 39
4.1 Introduction………………………… 40
4.2 Circuit Description……………….. 40
4.2.1 Skew Detection Step……. 44
4.2.2 Skew Correction Step…… 48
4.2.3 Period Detection Step… 49
4.2.4 Duty Cycle Setting Step… 53
4.2.5 Final Setting Step…….. 53
4.3 Performance Analysis…………….. 54
4.4 Simulation Results………………... 57
4.5 Experimental Results………………... 59
4.6 Summary…………………………….. 65

5. ALL-DIGITAL FAST-LOCKED SYNCHRONOUS DUTY-CYCLE CORRECTOR 67
5.1 Introduction……………………... 68
5.2 Circuit Description……………..….. 69
5.2.1 Clock Generator and Interpolator… 70
5.2.2 Synchronization Circuit…….………….. 72
5.3 Performance Analysis……………... 75
5.4 Simulation Results…………………… 78
5.5 Experimental Results………………… 80
5.6 Summary….………………………….. 84

6. A WIDE-RANGE ALL-DIGITAL DUTY CYCLE CORRECTOR WITH A CLOSED-LOOP MONITOR 85
6.1 Introduction……………………….... 86
6.2 Circuit Description…………….….. 87
6.2.1 Buffer……………………... 89
6.2.2 Timing Control Unit (TCU)…90
6.2.3 Time-to-Digital Converter (TDC).… 91
6.2.4 Code Generator…………... 93
6.2.5 Period Monitor…………… 96
6.3 Simulation Results……...……………. 97
6.4 Experimental Results………………. 99
6.5 Summary…………...………………... 105

7. CONCLUSIONS………………………….……. 107

Bibliography ………………………………….. 111

Publication List ……………………………………… 117

[1]P. K. Hanumolu, B. Casper, R. Mooney, G. Y. Wei and U. K. Moon, “Analysis of PLL clock jitter in high-speed serial links“, IEEE Trans. on Circuits and Systems—II: Analog and Digital Signal Processing, vol. 50, pp. 879-886, Nov. 2003

[2]J. Kim, M. A. Horowitz, and G. Y. Wei, “Design of CMOS adaptive-bandwidth PLL/DLLs: a general approach”, IEEE Trans. on Circuits and Systems—II: Analog and Digital Signal Processing, vol. 50, pp. 860-869, Nov. 2003

[3]B. Razavi, Monolithic phase-locked loops and clock recovery circuits: theory and design, IEEE Press, 1996.

[4]R. E. Best, Phase-locked loops: theory, design and applications, New York: McGraw-Hill, 1998.

[5]J. Lee and B. Kim, “A low-noise fast-lock phase-locked loop with adaptive bandwidth control”, IEEE J. Solid-State Circuits, vol. 35, no. 8, pp. 1137-1145, Aug. 2000.

[6]J. G. Maneatis, “Low jitter process-independent DLL and PLL based on self-biased techniques”, IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1723-1732, Nov. 1996.

[7]M.-J Edward Lee, W. J. Dally, T. Greer, H. Ng, R. Farjad-Rad, J. Poulton and R. Senthinathan, “Jitter transfer characteristics of delay-locked loops - theories and design techniques”, IEEE J. Solid-State Circuits, vol. 38, no. 4, pp. 614-621, April 2003.

[8]Y. Okajima, M. Taguchi, M. Yanagawa, K. Nishimura, and O. Hamada, “Digital delay locked loop and design technique for high-speed synchronous interface”, IEICE Trans. Electron., vol. E79-C, pp.798-807, June 1996.

[9]H. Sutoh, K. Yamakoshi, and M. Ino, “Circuit technique for skew-free clock distribution”, in IEEE Custom Integrated circuits conf., 1995, pp163-166.

[10]G.-K. G.. K. Dehng, J. M. Hsu, C. Y. Yang, and S. I. Liu, “Clock-deskew buffer using a SAR-controlled delay-locked loop”, IEEE J. Solid-State Circuits, vol. 35, no. 8, pp. 1128-1136, Aug. 2000.

[11]J. Lee and B. Kim, “A low-noise fast-lock phase-locked loop with adaptive bandwidth control”, IEEE J. Solid-State Circuits, vol. 35, no. 8, pp. 1137-1145, Aug. 2000.

[12]K. Nakamura, M. Fukaishi, Y. Hirota, Y. Nakazawa, and M. Yotsuyanagi, “A CMOS 50% duty cycle repeater using complementary phase blending”, in Symp. on VLSI Circuits Dig. Tech. Papers, June 2000, pp. 48-49.

[13]T. Ogawa and K. Taniguchi, “A 50% duty-cycle correction circuit for PLL output”, in Pro. IEEE Int. Symp. Circuits and systems, vol. 4, 2002, pp. 21-24.

[14]Y. Moon, J. Choi, K. Lee, D.-K. Jeong, and M. K. Kim, “An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance”, IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 377-384, Mar. 2000.

[15]F. Mu and C. Svensson, “Pulsewidth control loop in high-speed CMOS clock buffers”, IEEE J. Solid-State Circuits, vol. 35, pp. 134-141, Feb. 2000.


[16]P. H. Yang and J. S. Wang, “Low-voltage pulsewidth control loops for SOC applications”, IEEE J. Solid-State Circuits, vol. 37, pp. 1348-1351, Oct. 2002.

[17]W. M. Lin and H. Y. Huang, “A low-jitter mutual-correlated pulsewidth control loop circuit”, in Proc. IEEE int. Conf. Systems-on-Chip, 2003, pp. 301-304.

[18]S. R. Han and S. I. Liu, “A 500-MHz-1.25-GHz fast-locking pulsewidth control loop with presettable duty cycle”, IEEE J. Solid-State Circuits, vol. 39, pp. 463-468, March 2004.

[19]H. Jin and E. K. F. Lee, “A digital-background calibration technique for minimizing timing-error effect in time-interleaved ADC’s”, IEEE Trans. Circuits and Systems, Pt-II, vol. 47, pp. 603-613, July 2000.

[20]G. Manganaro, S. U. Kwak and A. R. Bugeja, “A dual 10-b 200-MSPS pipelined D/A converter with DLL-based clock synthesizer”, IEEE Journal of Solid-State Circuits, SC-39, pp. 1829- 1838, Nov. 2004.

[21]S. Karthikeyan, “Clock duty cycle adjuster circuits for switched capacitor circuits”, Electronics Letters, vol 38, pp. 1008-1009, Aug. 2002.

[22]J. M. Rabaey, A. Chandrakasan and B. Nikolic, “Digital Integrated Circuits: A Design Perspective, 2nd ed. Englewood Cliffs, NJ: Prentice-Hall, 2003.

[23]M. Mota and J. Christiansen, “ A four-channel self-calibrating high-resolution time to digital converter,” in Proc. IEEE Int. Conf. Electronics, Circuits, Systems, pp 409-412, 1998.

[24]R. B. Waston, Jr., and R. B. Iknaian, “Clock buffers chip with multiple target automatic skew compensation,” IEEE J. Solid-State Circuits, vol. 30, pp. 1267-1276, Nov. 1995.

[25]H. Sutoh, K. Yamakoshi, and M. Ino, “Circuit techniques for skew-free clock distribution”, in IEEE Custom Integrated Circuit Conf., 1995, pp. 163-166.

[26]S. Tanoi, T. Tanabe, K. Takahashi, S. Miyamoto and M. Uesugi, ”A 250-622MHz deskew and jitter-suppressed clock buffer using a frequency- and delay-locked two loop architecture”, in Symp. VLSI circuits, pp. 85-86, June 1995.

[27]Y. Jung, S. Lee, D. Shim, W. Kim, C. Kim and S. Cho, “A low jitter dual loop DLL using multiple VCDLs with duty cycle corrector”, in Symp. VLSI circuits, pp. 50-51, June 2000.

[28]T. Saeki, et al., “A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay”, IEEE J. Solid-State Circuits, vol. 31, pp. 1656-1668, Nov. 1996.

[29]K. Sung, B. Yang and L. Kim, “Low power clock generator based on area-reduced interleaved synchronous mirror delay”, Electronics Letters, vol 38, pp. 399-400, April 2002.

[30]T. Saeki, K. Minami, H. Yoshoda, and H. Suzuki , “A direct-skew-detect synchronous mirror delay for application-specific integrated circuits”, IEEE J. Solid-State Circuits, vol. 34, pp. 372-379, March 1999.

[31]Y. M. Wang and J. S. Wang, “A low-power half-delay-line fast skew-compensation circuit”, IEEE J. Solid-State Circuits, vol. 39, pp. 906-918, June 2004.

[32]M. Mano, “Computer Engineering: Hardware Design”, Prentice-Hall, INC. 1988.


[33]T. H. Lee, K. S. Donnelly, J. T. C. Ho, J. Zerbe, M. G. Johnson and T. Ishikawa, “A 2.5V CMOS delay-locked loop for 18Mbit 500megabytes/s DRAM”, IEEE J. Solid-State Circuits, vol.29, pp.1491-1496, Dec. 1994.

[34]K. H. Kim, G. H. Cho, J. B. Lee, and S. I. Cho, ”Built-in duty cycle corrector using coded phase blending scheme for DDR/DDR2 synchronous DRAM application”, in Digest of Technical Papers, Symposium on VLSI circuits, pp. 287-288, June 2003.

[35]Y. C. Jang, S. J. Bae and H. J. Park, “CMOS digital duty cycle correction circuit for multi-phase clock”, Electronics Letters, vol. 39, pp. 1383-1384, Sept. 2003.

[36]J. J. Nam and H. J. Park, “An all-digital CMOS duty cycle corrector circuit with a duty-cycle correction range of 15-to-85% for multi-phase applications”, IEICE Trans. Electron., vol. 88, pp. 773-777, April 2005.

[37]Y. M. Wang and J. S. Wang, “An All-digital 50% duty-cycle corrector”, in IEEE Int. Circuits and Systems Symp., vol. 2, pp. 925-928, May 2004.

[38]C. Jeong, C. Yoo, J. J. Lee and J. Kih, “Digital delay locked loop with open-loop digital duty cycle corrector for 1.2Gb/s/pin double data rate SDRAM”, Proceeding of the 30th European Solid-State Circuits Conference, pp. 379-382, Sept. 2004

[39]B. W. Garlepp, K. S. Donnelly, J. Kim, P. S. Chau, J. L. Zerbe, C. Huang, C. V. Tran, C. L. Portmann, D. Stark, Y.-F. Chan, T. H. Lee, and M. A. Horowitz, “A portable digital DLL for high-speed CMOS interface circuits”, IEEE J. Solid-State Circuits, vol. 34, pp. 632 -644, May 1999.


[40]S. Kao and S. I. Liu, “All-digital fast-locked synchronous duty-cycle corrector,” IEEE Trans. Circuits and Systems- II: Express Briefs, vol.53, pp.
1363-1367, Dec. 2006.