跳到主要內容

臺灣博碩士論文加值系統

(98.82.120.188) 您好!臺灣時間:2024/09/15 16:18
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:黃舜鴻
研究生(外文):Shun-Hung Huang
論文名稱:蕭特基能障鍺通道電晶體及鎳鍺化物隨溫度變化之關係與金氧半電容之應變效應
論文名稱(外文):Schottky barrier Germanium Channel MOSFET and Temperature dependence of Nickel-Germanide Formation andStrain Induced effect on MOS Capacitor
指導教授:劉致為
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:英文
論文頁數:112
中文關鍵詞:金氧半電晶體鍺通道場效電晶體蕭特基能障鎳金屬鍺化物
外文關鍵詞:MOSFETGe-channel MOSFETSchottky-barrierNickel-germanideStrain
相關次數:
  • 被引用被引用:0
  • 點閱點閱:164
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
本文中,我們將介紹並探討場效電晶體技術發展中三種重要的議題:蕭特基位能障鍺通道電晶體、鎳金屬鍺化物 及應力效應。
在矽基板上成長一層磊晶應變鍺,並在應變鍺上面成長矽保護層,如此的結構可實現鍺通道的電晶體;而源/汲極則使用鉑金屬來形成P型電晶體的蕭基位能障。我們使用三道光罩的製程來製作元件,並且改善了先前一道光罩製程的缺失。順道提供一些有用的概念以及參數的調整使製程的實行能夠更加完善。
用在以鍺為基底之場效電晶體的電極材質結構中,鎳鍺化合物因其多樣的優點而非常適合用作在以鍺為基底元件電極結構上。我們將說明在不同方向的鍺基底上會隨不同退火之溫度而形成不同鎳鍺化合物並討論之。
我們建構了一種機制來施加外在單軸或雙軸的伸展應力。在應力之下,量測金氧半電容元件(在(100)方向的矽基板上)的平帶電壓的移動,可以觀察到矽的導電帶往下移動以及價電帶往上移動。此外,我們也在(110)方向的矽基板上作了相同的實驗,並且討論其在雙軸的伸展應力下金氧半電容的平帶電壓的移動情況。
In this work, we will introduce and discuss three important topics of advancement of metal-oxide-semiconductor field-effect transistors technology which are Schottky-barrier germanium channel MOSFET, Nickel-germanide, and Strain induced effect.
By using Si-cap/ε-Ge/Si substrate, we can get Germanium channel. And Platinum (Pt) is deposited as metal Schottky-barrier source/drain of p-type MOSFET. The devices are fabricated by three mask process and overcome some shortcomings from one mask process. Some useful concepts and adjustments are also provided to improve the performance of the process.
Formation of electrical contacts in Ge-based MOSFETs have been studied, nickel monogermanide (NiGe) is certainly advantageous for its use as contact material in Ge-based devices. The variation of Ni/Ge structure on different orientation substrate as a function of annealing temperature will be shown and discussed.
We built up a mechanical setup to apply external uniaxial and biaxial tensile strain. By measuring flat-band voltage shift of MOS capacitor on the (110) orientation Si under strain conditions, the reduction of conduction band and the upward shift of valence band edge were observed. Moreover, we done the same experiment on the (110) orientation Si and discuss flat-band voltage shift of MOS capacitor under biaxial strain.
Contents

Chapter 1 Introduction
1.1 Motivation 1
1.1.1 Schottky-barrier Germanium channel pMOSFETs 3
1.1.2 Nickel-Germanide 4
1.1.3 Strain technology 5
1.2 Thesis Organization 5
References 7

Chapter2 Three mask process for Germanium channel
Schottky-barrier pMOSFET
2.1 Introduction 9
2.2 experiment 14
2.2.1 Substrate fabrication 18
2.2.2 Lithography 21
2.2.3 Source/Drain or Gate metal deposition 28
2.2.4 Metal lift-off 29
2.2.5 Oxide deposition and etching 32
2.3 Results and Discussion 34
2.4 Conclusion 42
References 43

Chapter 3 Temperature dependence of Nickel-Germanide formation
3.1 Introduction 45
3.2 Experiment 47
3.3 Results and Discussion 48
3.3.1 Sheet resistance 48
3.3.2 Phase identification 49
3.3.3 Surface roughness 60
3.3.4 I-V characteristic 65
3.4 Conclusion 70
References 71

Chapter 4 Strain-induced effects on MOS capacitor
4.1 Introduction 73
4.2 Strain theory 75
4.2.1 Raman spectroscopy 75
4.2.2 Electron affinity variation and bandgap narrowing with strain 77
4.2.3 Relationship between Ef and Ec (or Ev) under tensile stress 84
4.3 Experiment 87
4.3.1 External mechanical strain setup gear (uniaxial & biaxial ) 87
4.3.2 Substrate preparation and Raman measurement 89
4.3.3 MOS capacitor device fabrication and C-V measurement 92
4.4 Results and Discussion 94
4.4.1 Strain-induced Raman shift 94
4.4.2 Flat-band voltage shifts with strain 96
4.5 (110) substrate biaxial strain 102
4.5.1 Sample cutting 102
4.5.2 Strain-induced Raman shift for (110) sub 103
4.5.3 C-V characteristic variation for (110) substrate 104
4.5.4 Flat-band voltage shifts with strain 106
4.6 Conclusion 107
References 108

Chapter 5 Summary and Future Work
5.1 Summary 110
5.2 Future Work 112
References CH2
[1] S. M. Sze and J. C. Irvin, “Resitivity, mobility and impurity levels in GaAs, Ge, and Si at 300°K,” Solid State Electron., vol. 11, pp. 599-602, 1968.
[2] M. L. Lee and E. A. Fitzgerald, “Optimized strained Si / strained Ge dual-channel heterostructures for high mobility P- and N-MOSFETs,” IEDM Tech. Dig., pp. 429-432, 2003.
[3] H. Shang, J. O. Chu, S. Bedell, E. P. Gusev, P. Jamison, Y. Zhang, J. A. Ott, M. Copel, D. Sadana, K. W. Guarini, and M. Ieong, “Selectively formed high mobility strained Ge PMOSFETs for high performance CMOS,” IEDM Tech. Dig., pp. 157-160, 2004.
[4] M.-A. Nicolet and W.-S. Liu, “Oxidation of GeSi,” Microelectronics Eng., vol.28, pp. 185-191, 1995.
[5] K. Prabhakaran and T. Ogino, “Oxidation of Ge(100) and Ge(111) surfaces,” Surf. Sci., vol. 325, pp. 263-271, 1995.
[6] “Front end processes,” in International Technology Roadmap for Semiconductors 2003 Edition. Austin, TX: Semiconductor Industry Assoc., 2003.
[7] Y. Nishi, “Insulated gate field effect transistor and its manufacturing
method,” Patent 587 527, 1970.
[8] M. P. Lepselter and S. M. Sze, “SB-IGFET: An insulated-gate field-effect transistor using Schottky barrier contacts for source and drain,” Proc. IEEE, vol. 56, no. 8, pp. 1400-1402, Aug. 1968.
[9] E. Dubois and G. Larrieu, “Measurement of low Schottky barrier heights applied to S/D metal-oxide-semiconductor field effect transistors,” J. Appl. Phys., vol. 96, no. 1, pp. 729-737, Jul. 2004.
[10] V. W. L. Chin, J. W. V. Storey, and M. A. Green, “Characteristics of p-type PtSi Schottky diodes under reverse bias,” J. Appl. Phys., vol. 68, pp. 4127-4132, Oct. 1990.
[11] S. Zhu, J. Chen, M.-F. Li, S. J. Lee, J. Singh, C. X. Zhu, A. Du, C. H. Tung, A. Chin, and D. L. Kwong, “N-type Schottky barrier S/D MOSFET using Ytterbium silicide,” IEEE Electron Device Lett., vol. 25, no. 8, pp. 565-567, 2004.
[12] M. Jang, Y. Kim, J. Shin, and S. Lee, “Characterization of erbiumsilicided Schottky diode junction,” IEEE Electron Device Lett., vol. 26, no. 6, pp. 354-356, 2005.
[13] Chi On Chui, H. Kim, D. Chi, B. B. Triplett, P. C. McIntyre, and K. C. Saraswat, “A sub-400°C Germanium MOSFET technology with high-k dielectric and metal gate,” IEDM Tech. Dig., pp. 437-440, 2002.
[14] S. Zhu, et al., “Schottky-barrier S/D MOSFETs with high-k gate dielectrics and metal-gate electrode,” IEEE Electron Device Lett., vol. 25, pp. 268-270, 2004.
[15] H. Shang, J. O. Chu, X. Wang, P. M. Mooney, K Lee, J. Ott, K. Rim, K. Chan, K. Guarini, M. Ieong, “Channel Design and Mobility Enhancement in Strained Germanium Buried Channel MOSFETs.” P204-205
[16] John M. Larson and John P. Snyder, “Overview and status of metal S/D Schottky-barrier MOSFET technology,” IEEE Transactions on Electron Device, vol.53, no.5, pp. 1048-1058, 2006

References CH3
[1] S. C. Martin, L. M. Hitt, and J. J. Rosenberg, “p-channel Germanium MOSFETs with high channel mobility,” IEEE Electron Device Lett., vol. 10, no. 7, pp. 325-326, 1989.
[2] K. Ikeda, Y. Yamashita, N. Sugiyama, “Modulation of NiGe/Ge Schottky barrier height by sulfur segregation during Ni germanidation,” Appl. Phys. Lett., vol. 88, 152115, 2006.
[3] J. Y. Spann, R. A. Anderson, T. J. Thornton, G. Harris, S. G. Thomas, and C. Tracy, “Characteristic of Nickel Germanide Thin Films for Use as Contacts to p-channel Germanium MOSFETs,” IEEE Electron Device Lett., vol. 26, no. 3, pp. 151-153, 2005.
[4] H. Shang, H. Okorn-Schimdt, J. Ott, P. Kozolowski, S. Steen, E. C. Jones, H. S. P. Wong, and W. Hanesch, “Electrical characterization of germanium p-channel MOSFETs,” IEEE Electron Device Lett., vol. 24, no.3, pp. 242-244, 2003.
[5] C. O. Chui, H. Kim, D. Chi, B. B. Triplett, P. C. McIntyre, and K. C. Saraswat, “A sub-400°C Germanium MOSFET technology with high-k dielectric and metal gate,” IEDM Tech. Dig., pp. 437-440, 2002.
[6] D. S. Yu, C. H. Huang, M.F. Li, B. J. Cho, and D. L. Kwong, “Al2O3 –Ge-On-Insulator n- and p- MOSFETs With Fully NiSi and NiGe dual Gates,” IEEE Electron Device Lett., vol. 25, no.3, pp. 138-140, 2004.
[7] A. Ritenour, S. Yu, M. L. Lee, N. Lu, W. Bai, A. Pitera, E. A. Fitzgerald, D. L. Kwong, and D. A. Antoniadis, “Epitaxial Strained Germanium p-MOSFETs with HfO2 Gate Dielectric and TaN Gate Electrode,” IEDM Tech. Dig., pp. 433-436, 2003.
[8] S. Zhu, R. Li, S. J. Lee, M. F. Li, A. Du, J. Singh, C. Zhu, A. Chin, and D. L Kwong, “Germanium pMOSFETs With Schottky-Barrier Germanide S/D, High-k Gate Dielectric and Metsl Gate,” IEEE Electron Device Lett., vol. 26, no.2, pp. 81-83, 2005.
[9] D. Z. Chi, R. T. P. Lee, S. J. Chua, S. J. Lee, S. Ashok, and D. L. Kwong, “Current-voltage characteristics of Schottky barriers with barrier heights larger than the semiconductor band gap : The case of NiGe/ n-(001) Ge contact,” J. of Appl. Phys. Lett., vol. 97, 113706, 2005
[10] T. Deegan et al., Applied Surface Science 123/124, 66 (1998)
[11] JCPDS diffraction file 07-0297 (NiGe).
[12] S. Zhu, A. Nakajima, Y. Yokoyama, and K. Ohkura, “Temperature Deoendence of Ni-Germanide Formed by Ni-Ge Solid-State Reaction” 5th International Workshop on Junction Technology, 2005.
[13] T. Jarmar, “High-Resolution Studies of Silicide-films for Nano IC-Component,” Acta Universitatis Upsaliensis, 2005.
[14] S. L. Zhang, M. Ostling, “Metal Silicides in CMOS Technology: Past, Present and Future Trends,” Critical Reviews in Solid State and Materials Sciences, 28, 1, 2003.
[15] F. Nemouchi, D. Mangelinck, C. Bergman, G. Clugnet, P. Gas, and J. L. Labar, “Simultaneous growth of Ni5Ge3 and NiGe by reaction of Ni film with Ge,” Appl. Phys. Lett., vol. 89, 131920, 2006.
[16] R. T. P. Lee, D. Z. Chi, M.Y. Lai, N. L. Yakovlev, and S. J. Chua, “Effects of Incorporation in Ni on Silicidation Reaction and Structural/Electrical Properties of NiSi,” Electrochem. Soc. 151, G642,2004.
[17] S. Gaudet, C. Lavoie, C. Detavernier, and P. Desjardins, “Germanide phase formation and texture,” 3rd International SiGe Technology and Device Meeting (ISTDM), New Jersey, May 15-17, pp. 22. 2006.
[18] J. K. Patterson, B. J. Park, K. Ritley, H. Z. Xiao, L. H. Allen, and A. Rockett, “Kinetics of Ni/a-Ge bilayer reactions,” Thin Solid Films, Vol. 253, pp.456-461, 1994.

References CH4
[1] “ Front end processes,” in International Technology Roadmap for Semiconductor 2003 Edition. Austin, TX: Semiconductor Industry Assoc., 2003.
[2] M. Rodder, “45nm CMOS: Device architecture and roadmap,” in IEDM Tech. Dig. Tutorial, 2004, pp. 1-61.
[3] C. W. Liu, S. Maikap, and C.-Y. Yu, IEEE Circuits and Devices Magazine, May/June, pp. 21-36, 2005.
[4] S. Takagi, J. L. Hoyt, J. J. Welser, and J. F.Gibbons, “Comparative study of phononlimited mobility of two-dimensional electrons in strained and unstrained-Si metal-oxide-semiconductor field-effect transistors,” Journal of Applied Physics. vol. 80, pp. 1567-1577, 1996.
[5] S. Thompson et al., “ A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 mm 2 SRAM cell,” in IEDM Tech. Dig., 2002, pp.61-64.
[6] S. E. Thompson et al., “ A logic nanotechnology featuring strained silicon,” IEEE Electron Device Lett., vol. 25, pp. 191-193, Apr. 2004.
[7] K. Rim et al., “Fabrication and mobility characteristics of ultra-thin strained Si directly on insulator (SSDOI) MOSFETs,” in IEDM Tech. Dig., 2003, pp. 49-52.
[8] S. Maikap, M. H. Liao, F. Yuan, M. H. Lee, C.-F. Huang, S. T. Chang, and C. W. Liu, Tech. Dig. – Int. Electron Devices Meet. 233 (2004).
[9] M. H. Liao, S. T. Chang, M. H. Lee, S. Maikap, and C. W. Liu, Journal of Applied Physics. vol. 98, pp. 066104-066106, 2005.
[10] Y. Hida, T. Tamagawa, H. Ueba, and C. Tatsuyama, Journal of Applied Physics. vol. 67, pp. 7274-7277, 1990.
[11] EMIS Datareviews Series No. 20, Properties of Crystalline Silicon, edited by R. Hull (1999).
[12] W. Zhang and J. G. Fossum, “On the threshold voltage of strained-Si–Si1-xGex MOSFETs,” IEEE Trans. Electron Devices, vol. 52, no.2, pp. 263-268, 2005.
[13] J-S Lim, S. E. Thompson, J. G. Fossum, “Comparison of threshold-voltage shifts for uniaxial and biaxial tensile-stressed n-MOSFETs,” IEEE Electron Device Lett., vol. 25, no. 11, pp. 731-733, 2004.
[14] M. V. Fischetti and S. E. Laux, “Band structure, deformation potentials, and carrier mobility in strained-Si, Ge, and SiGe alloys,” Journal of Applied Physics., vol. 80, pp. 2234-2252, 1996.
[15] Mehmet C. Ozturk, “Short course- channel, source/drain and contact engineering for 45nm,” in IEDM, 2004.
[16] C. Herring and E. Vogt, “Transport and deformation-potential theory for many-valley semiconductors with anisotropic scattering,” Phys. Rev., vol. 101, pp. 944-961, 1956.
[17] I. Balslev, “Influence of uniaxial stress on the indirect absorption edge in silicon and germanium,” Phys. Rev., vol. 143, pp. 636-647, 1966.
[18] C. G. VandeWalle and R. M. Martin, “Theoretical calculations of heterojunction discontinuities in the Si/Ge system,” Phys. Rev. B, Condens. Matter, vol. 34, pp. 5621-5634, 1986.
[19] H. Miyata, T. Yamada, and D. K. Ferry, “Electron transport properties of a strained-Si layer on a relaxed Si1-xGex substrate by Monte Carlo simulation,” Appl. Phys. Lett., vol. 62, pp. 266-2663, 1993.
[20] K. Rim, J.Welser, J. L. Hoyt, and J. F. Gibbons, “Enhanced hole mobilities in surface-channel strained-Si p-MOSFETs,” in IEDM Tech. Dig., pp. 517-520, 1995.
[21] M. H. Liao, P.-S. Kuo, S.-R. Jan, S. T. Chang, and C. W. Liu,” Strained Pt Schottky diodes on n-type Si and Ge,” Appl. Phys. Lett. 88, 143509 (2006).
[22] Ashcroft and Mermin, Solid state physics, pp. 32-38. (Harcourt, 1975).
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top