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研究生:張呈毓
研究生(外文):Cheng-Yu Chang
論文名稱:應用於Serial-ATA之6GHz低相位抖動展頻時脈產生器之設計與實作
論文名稱(外文):Design and Implementation of a Low-Jitter 6GHz Spread Spectrum Clock Generator for Serial-ATA
指導教授:陳少傑陳少傑引用關係
指導教授(外文):Sao-Jie Chen
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:英文
論文頁數:79
中文關鍵詞:展頻時脈展頻時脈產生器鎖相迴路除小數式三角積分調變器電磁干擾相位抖動小數突波壓控振盪器
外文關鍵詞:SSCSSCGSerial ATAPLLFractional-NΔ-Σ modulatorEMIJitterFractional spursVoltage Controlled Oscillator
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EMI (Electro-Magnetic Interference) causes more destruction to the transmitting signal since the operating frequency is higher than before. Spread spectrum clocking (SSC) is a method that can reduce the EMI effectively. This method is more and more popular since it is easy to design and suitable for integrated IC. Serial ATA is a high speed external mass storage device having the SSC specifications as following: a triangular modulation profile with down spread, a 5000 ppm frequency deviation, a 30~33KHz modulation frequency, an EMI reduction larger than 7dB, and a 3ps RMS jitter @ 250 cycles.
Our research is stressed on low-jitter design. Due to the higher operating frequency requirement, design with low-jitter performance becomes more and more important and thus more difficult to realize. VCO phase noise dominates the jitter performance of PLLs. Therefore, we proposed a LC tank VCO with low phase noise characteristic. The simulation results show that the phase noise is -119.8dBc/Hz @1MHz offset voltage and FoM is -190.8.
In this Thesis, a spread spectrum clock generator (SSCG) modulated by a divider is presented. The PLL is fabricated in a 0.18μm CMOS process and the whole SSCG system is integrated and tested on an FPGA board. The simulation results show that all specifications of the Serial ATA have been achieved in our system and the jitter measurement shows that the RMS jitter is 0.4ps @ 250 cycles.
TABLE OF CONTENTS
ABSTRACT i
LIST OF FIGURES v
LIST OF TABLES ix
CHAPTER 1 INTRODUCTION 1
1.1 Motivation 1
1.2 Thesis Organization 2
CHAPTER 2 BASIC OF SPREAD SPECTRUM CLOCKING 5
2.1 Specification of Serial ATA for SSC 5
2.2 Fundamental Theory of SSC 6
2.3 Types of SSC Implementation 8
2.4 Jitter Performance 10
CHAPTER 3 FRACTIONAL-N PLL USING Δ-Σ MODULATOR 13
3.1 Principle of Phase-Locked Loop 13
3.2 Analysis of Phase-Locked Loop 14
3.2.1 Voltage Controlled Oscillator 14
3.2.2 PFD with Charge Pump and Loop Filter 15
3.2.3 Linear Model of PLL 17
3.2.4 Phase Noise in PLL 19
3.3 Fractional-N Frequency Synthesis 21
3.3.1 Pulse Swallow 22
3.3.2 Fractional Spurs 24
3.4 Δ-Σ Modulator 26
3.5 Third-Order MASH Δ-Σ Modulator 29
CHAPTER 4 DESIGN OF SPREAD SPECTRUM CLOCK GENERATOR 33
4.1 System Architecture 33
4.2 Voltage Controlled Oscillator 34
4.2.1 LC-VCO Versus Ring-VCO 35
4.2.2 VCO Phase Noise 35
4.2.3 LC-VCO Technique 37
4.2.4 A New LC-VCO with Back-Gate Tuning Technique 39
4.3 Phase/Frequency Detector 40
4.4 Charge Pump 41
4.5 Programmable Charge Pump 43
4.6 Multi-Modulus Divider 44
4.7 Loop Filter 45
4.8 MASH 1-1-1 Δ-Σ Modulator 49
4.9 Triangular Generator 52
CHAPTER 5 SIMULATION RESULTS OF SPREAD SPECTRUM CLOCK GENERATOR 55
5.1 SSCG Behavior Simulation 55
5.2 Circuit Level Simulation 58
5.2.1 Voltage Controlled Oscillator 59
5.2.2 Phase/Frequency Detector and Charge Pump 62
5.2.3 Prescaler 64
5.2.4 Multi-Modulus Divider 64
5.2.5 Closed-Loop Simulation of PLL 65
5.2.6 PLL Implementation 67
5.3 MASH 1-1-1 and Triangular Generator 69
5.4 Closed-Loop Simulation of SSCG 71
CHAPTER 6 CONCLUSION 75
REFERENCE 77
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