臺灣博碩士論文加值系統

隨著傳輸速率的增加，傳輸線損耗對於信號傳輸的影響將會更加嚴重，準確的量測數位訊號資料也將會越來越困難。所以瞭解有損傳輸線的理論，將會成為高速數位系統設計的一個重要課題。本論文說明了傳輸線衰減的物理現象，提出一種可以有效對於傳輸線損耗進行補償的設計方法，並且使用一精心設計的等化器來消除信號上升時間和下降時間的衰減、額外的抖動現象，甚至其他由於傳輸線損耗所造成訊號完整度變差的結果。

With increasing bit rates, accurate measurement of the signal integrity of digital data streams becomes more difficult, which is more influenced by the presence of interconnected loss。A good understanding of the principles of transmission line loss becomes therefore essential for high speed digital system design. This thesis summarizes the physics of transmission line loss and presents the design of a device for loss compensation. The Usage of a well-designed compensation filter eliminates rise and fall time degradation, additional jitter and other deteriorated signal integrity introduced by the lossy interconnection.

目 錄



第一章 簡介 ................................. 1
1-1 研究動機與目的 ........................1
1-2 文獻探討 ..............................2
1-3 章節概要 ..............................3
1-4 成果貢獻 ..............................3

第二章 傳輸線損耗原理與相關規範 ..............4
2-1 前言 ..................................4
2-2 傳輸線基本原理 ........................4
2-3 有損傳輸線 ............................7
2-3-1 導線與介質之直流損耗 ............7
2-3-2 趨膚效應.........................8
2-3-3 與頻率相關的介質損耗............12
2-4 眼圖相關參數..........................14
2-5 PCI Express Π 信號規範介紹............16
2-6 碼際干擾 .............................17
2-7 數位訊號頻譜分析......................18

第三章 等化器補償原理........................20
3-1 理論說明..............................20
3-2 最佳補償後S參數與眼圖.................24
3-2-1 模擬方式........................24
3-2-2 模擬結果........................24

第四章 補償電路的設計........................31
4-1 RL等化器 .............................31
4-2 單根傳輸線的最佳補償電路..............31
4-2-1 設計方法........................31
4-2-2 電路模擬........................33
4-3 差模結構傳輸線的最佳補償電路..........36
4-3-1 混合模態........................36
4-3-2 電路模擬........................37
4-4 與RLC等化器之比較.....................38

第五章 實驗與模擬之驗證......................42
5-1 實驗環境設定..........................42
5-2 單根傳輸線實驗........................44
5-2-1 實驗流程........................44
5-2-2 實驗結構 .......................45
5-2-3 實驗結果........................45
5-3 差模結構傳輸線實驗....................48
5-3-1 實驗流程 .......................48
5-3-2 實驗結構 .......................48
5-3-3 實驗結果 .......................49
第六章 結論與未來工作........................52

參考文獻.....................................53

[1]K. Yamagishi and A. Saito, “Methods of eye-pattern window improvement using reflections caused by impedance mismatch post-emphasis technique,” : Electrical Performance of Electronic Packaging, 2005. IEEE 14th Topical Meeting on, pp. 209-212.

[2]K. J. Han, H. Takeuchi, E. Engin and M. Swaminathan, ”Eye-pattern improvement for design of high-speed differential links using passive equalization,” Topical Meeting on Electrical Performance of Electronic Packaging, 2006.
[3]W. Humann, and Agilent Technologies, “Compensation of transmission line loss for Gbit/s test on ATEs,” IEEE International Test Conference, 2002, pp. 430-437.
[4]J. D. Geest, S. Sercu, and J. Nadolny, “How to make optimal use of signal conditioning in 40 Gb/s copper interconnects”, DesignCon 2003, High-Performance System Design Conference, Jan. 2002.
[5]W. T. Beyene, N. Cheng, J. Feng, H. Shi, D. Oh, and C. Yuan, ” Performance analysis of multi-gigahertz parallel bus with transmit pre-emphasis equalization,” IEEE MTT-S International Microwave Symposium digest, 2005, vol. 4, pp.1849-1852.
[6]D. M. Pozar, Microwave Engineering, 2nd Ed., John Wiley & Sons, Inc., 1998, Ch. 2.
[7]S. H. Hall, G. W. Hall and J. A. McCall, High-Speed Digital System Design, John Wiley & Sons, Inc. Publication, 2000, pp.74-88.
[8]H. Yue, K. L. Virga, J. L. Prince, ”Dielectric constant and loss tangent measurement using a stripline fixture,” IEEE Trans. Comp. Package, Nov. 1998, pp.441-446.
[9]R. B. Wu, Time-domain simulation for transmission lines, Research Project under Grant NSC-80-0404-E002-36, 1990.
[10]G. Breed, “Analyzing signals using the eye diagram,” High Frequency Electronics, Nov.2005.
[11]N. Ou, Y. Farahmand, A. Kuo, S. Tabatabaei, and A. Ivanow, ”Jitter models for the design and test of Gbps-speed serial interconnects,” IEEE Design & Test of Computer, vol.9, no.4, July/August. 2004, pp.302-312.
[12]ADS tutorial.
[13]R. Vezina,”PCIe 2.0 5GHz signaling tutorial, ” Intel.
[14]S. H. Hall, G. W. Hall and J. A. McCall, High-Speed Digital System Design, John Wiley & Sons, Inc. Publication, 2000, pp. 95-97.
[15]C. R. Paul, Introduction to Electromagnetic Compatibility, 2nd Ed., John Wiley & Sons, Inc. Publication, 2006, pp.118-123.
[16]http://www.maxim-in.com

[17]HSPICE, Signal Integrity Guide, Version W-2005.03, March 2005.
[18]93年英業達結案報告,”第二章 傳輸線損耗補償”
[19]W.Fan, A. Lu, L. L. Wai, B. K. Lok, “Mixed-mode s-parameter characterization of differential structures,“ IEEE Electronics Packaging Technology Conf. p533-537,2003.