臺灣博碩士論文加值系統

隨著對無線通訊頻寬需求的升高，低成本高效能的微波積體電路的發展也漸趨熱門。傳統上，由於較好的元件特性，高頻積體電路多利用III-V半導體製程和SiGe BiCMOS製程實現。CMOS製程擁有低成本及高度整合性的優勢，似乎非常適合作此種電路的應用。然而，由於嚴重的基板損耗及較差的高頻特性，利用CMOS製程來實現這樣的系統，仍舊是項挑戰。因此，本論文將描述CMOS製程在設計高頻電路時的一些設計考量，接著提出不同的電路技巧來實現。
首先，本論文將介紹一應用於24-GHz之0.18-µm CMOS 傳送端/接收端切換器。為了提高關閉時的隔離度，提出ㄧ增加隔離度之電路技巧，藉由增加一額外開關，可有較佳的隔離度及合理的穿透損耗。此外，採用阻抗轉換的技巧來提升功率特性。量測結果顯示此單刀雙擲切換器在24-GHz可達到2.5-dB的穿透損耗及20-dB的隔離度，同時輸入及輸出反射損耗皆大於14-dB。且因採用阻抗轉換技巧，此切換器之輸入P1dB為24.2-dBm。
接著，本論文提出ㄧ應用於24-GHz之接收機架構。採用CMOS 0.18-µm製程，此接收機前端電路整合了低雜訊放大器、混波器及中頻放大器而擁有良好的轉換增益及低雜訊表現。量測結果顯示，在中頻頻率為4.82-GHz的情況下，此電路擁有28.4-dB的轉換增益及6-dB的雜訊，同時輸入反射損耗大於14-dB；而輸入P1dB及IIP3分別為-23.2及-13.0-dBm。在1.8-V的工作電壓下，功率消耗為54mW。
最後介紹一個適用於之前提出之24-GHz接收機架構之本地信號產生器。該電路由ㄧ19-GHz低相位雜訊壓控振盪器、除四除頻器、及相位調整器構成。藉由雜訊濾除技巧及電容回授以增加gm，可有效降低振盪器相位雜訊。此外，信號經除四除頻器及相位調整器調整後，可提供精準的四相位信號。

As the demands for wider bandwidth in wireless communication continue to expand, the development of low-cost and high-performance monolithic microwave integrated circuits (MMICs) have attracted great attention. Conventionally, the high-frequency integrated circuits were realized by III-V compound semiconductor and SiGe BiCMOS process due to their superior device performance. Owing to unparalleled advantages in both fabrication cost and denser integration, the CMOS technology appears to be well suited to implement these designs. However, it still remains a challenge for such RF building blocks to be integrated in a standard CMOS process due to its significant substrate losses and inferior high-frequency properties of the active devices. Consequently, this thesis describes the design consideration of the CMOS process for the individual building blocks then presents several novel circuit techniques to reach the requirements for the system designs.
First, a transmit/receive (T/R) switch for the 24-GHz ISM band application implemented in a standard 0.18-m CMOS process is demonstrated. A technique to enhance the isolation performance is proposed for the T/R switch. Reasonable isolation and insertion loss are achieved with an additional switch. Besides, impedance transformation networks (ITNs) is utilized to reduce the source and load impedance seen from the switch to increase the power handling capability. The fabricated SPDT (single-pole double-throw) switch at 24-GHz exhibits an insertion loss of 2.5 dB and an isolation of 20 dB while maintaining an input and output return loss better than 14 dB and 19 dB, respectively. Owing to the use of the ITNs, the measured Pin-1dB of the switch is 24.2 dBm.
Secondly, a receiver architecture is presented for operations at the 24-GHz frequency band. By monolithically integrating the LNA, the down-conversion mixer and the IF amplifiers, the receiver frontend is realized in a 0.18-m CMOS process, exhibiting enhanced circuit performance in terms of conversion gain and noise figure. With an IF frequency of 4.82-GHz, the fabricated circuit demonstrates a conversion gain of 28.4 dB and a noise figure of 6.0 dB while maintaining an input return loss better than 14 dB. The measured Pin-1dB and IIP3 of the receiver frontend are -23.2 and -13.0 dBm, respectively. The power consumption for the receiver frontend is 54mW at a supply voltage of 1.8 V,.
Finally, a signal generator which provides the required LO outputs for the proposed receiver architecture is presented. The proposed LO generator consists of a 19-GHz low-phase-noise voltage-controlled oscillator (VCO), a 4:1 frequency divider and a quadrature phase tuning circuit. With a noise filtering technique and gm-boosting capacitive feedback, the VCO exhibits low phase noise with adequate frequency tuning range. Besides, an interpolation technique, which is originally developed for ring oscillators, is adopted for the phase tuning the quadrature signal provided by the frequency divider to obtain accurate phases.

Table of Contents


Chapter1 Introduction 1
1.1 Motivation 1
1.2 Overview of the thesis 2

Chapter2 RF Receiver Fundamentals 3
2.1 Linearity 3
2.1.1 Gain Compression 4
2.1.2 Input-referred Third Order Intercept Point (IIP3) 5
2.1.3 Input-referred Second Order Intercept Point (IIP2) 7
2.2 Noise Figure 7
2.3 Sensitivity 9
2.4 Dynamic Range 10
2.5 Receiver Architectures 12
2.5.1 Superheterodyne Receiver 12
2.5.2 Direct-Conversion Receiver 14
2.5.3 Low-IF Receiver 16
2.5.4 Wideband-IF Receiver 17
2.5.5 Half-IF Receiver 18
2.6 Design Challenges of High Frequency Operation 20

Chapter 3 A 24-GHz Fully Integrated Single-Pole Double-Throw Switch in a 0.18-m CMOS Process 23
3.1 Introduction 23
3.2 The Proposed Isolation-Enhanced Switch 24
3.2.1 Isolation issue 24
3.2.2 The Proposed Isolation-Enhanced Technique 28
3.3 Circuit Design 31
3.4 The Experimental Results 34
3.5 Conclusion 37

Chapter 4 CMOS Wireless Receiver Front-End for 24-GHz ISM band Applications 39
4.1 Introduction 39
4.2 The Proposed Receiver Architecture 40
4.3 The Proposed Receiver Design 43
4.3.1 The Low-Noise Amplifier 43
4.3.2 The Mixer and the IF Amplifiers 47
4.4 The Experimental Results 51
4.5 Conclusion 54

Chapter 5 CMOS LO Signal Generator for 24-GHz Receiver
Applications 57
5.1 Introduction 57
5.2 The Proposed LO Signal Generator Architecture 58
5.3 The Proposed LO Signal Generator Design 62
5.3.1 The Voltage-Controlled Oscillator 62
5.3.2 The Divide-by-Four Circuit with Phase Tuning 65
5.3.3 The testing passive mixer 69
5.4 The simulation results and measurement setup 70
5.4.1 The simulation results 70
5.4.2 The measurement setups 72
5.5 Discussion and Conclusion 74

Chapter 6 Conclusion 75

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