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研究生:劉志祥
研究生(外文):Chee-Zxiang Liu
論文名稱:薄膜電晶體之應力效應與偏壓不穩定度
論文名稱(外文):Mechanical Strain Effect and Bias Temperature Instability of Thin Film Transistor
指導教授:劉致為
指導教授(外文):Chee-Wee Liu
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電機工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:英文
論文頁數:64
中文關鍵詞:應力薄膜電晶體偏壓不穩定度駝峰
外文關鍵詞:TFTspolyMechanical strainBTIhump
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摘要

低溫多晶矽薄膜電晶體是近年來應用平面顯示器中的一項重要技術,利用先進的雷射結晶法,使得可以在不耐高溫的玻璃基本上將矽基底重新結晶,藉以提高元件之載子移動率,除了可以使顯示器之開口率上升,提高對比度,並可以將外部驅動電路整合於玻離基板上,降低與外部接點數提升穩定度,更可以達到多功能面板的效果。
在本論文第二章中,我們介紹低溫多晶矽薄膜電晶體一般最常使用的製程方法及條件,並定義相關的元件參數,用以分析實驗之結果,
在本論文中,我們藉由施加機械應力,觀察低溫多晶矽薄膜電晶體電性之變化,並以各種物性測量,加以分析其元件內部產生變化之模型,有效達到利用外部應力,提升低溫多晶矽薄膜電晶體之載子移動率,在p通道低溫多晶矽薄膜電晶體施加垂直通道之應力與在n通道低溫多晶矽薄膜電晶體施加與通道平行之應力,會提升其載子移動率,在p通道低溫多晶矽薄膜電晶體施加平行通道之應力與在n通道低溫多晶矽薄膜電晶體施加與通道垂直之應力,會降低其載子移動率,詳細之物理機制都將於第三章介紹。
元件的穩定度,對於元件的生命週期,有十分重要的影響,在第四章中,我們在p通道低溫多晶矽薄膜電晶體閘極上,施加不同極性之電壓,觀察到兩種不同之現象,施加正偏壓時,可以看到其電性產生一駝峰效應,另外是負偏壓時,產生由於熱電洞打斷矽氫鍵結造成電性之變化,兩者對於元件之臨界電壓與驅動電流都有顯著之影響,在第四章中,將分別提供完整的分析及實驗資料。
Abstract

Low temperature polycrystalline silicon thin film transistors (LTPS TFTs) have been the trend of active matrix display driving circuitry, because of their high mobility, high aperture ratio, and the capability of integrating driver circuits into the panel frame. In the recent years, LTPS TFTs make a great strides by grown crystallize technology, Moreover, timer control circuit, source driver circuit, gate drive, level shift circuit and DC/DC convert circuit can be integrated on the glass substrate in the near future. How ever, the reliability issue and driving ability will be significant when the device sizes are scaled down.
In this thesis, the electrical characteristics, the current change of n-channel polycrystalline silicon thin-film transistors is analyzed experimentally and theoretically under different strain conditions, under the uniaxial strain parallel to the channel, the drain current will enhance, and the drain current will decrease on the uniaxial strain, recent year, strain enhance mobility technology has been extensively investigated for crystalline silicon, it has been attributed strain orientation and channel orientation, in low temperature poly silicon TFTs process, laser anneal induces crystalline has popularly used, after crystallization, silicon film will become poly silicon, and the inter grain orientation is depend grown temperature and crystallization method, and the TFTs are affected by strain.
In this thesis, negative and positive bias temperature instability of LTPS TFT have investigated, at first, the pMOS biased in high voltage induce hump issue, the threshold voltage will has a larger shift than negative bias stress, and the I-V curve will charge shape violent after short time positive bias stress, after stress, the hump will return to the origin condition slowly, but it can be accelerate by negative bias stress, in the experiment, we can explain the hump issue is caused by insulator thickness variation or fringe field, the high electronic field will induce external tuning current and generate more trap in device edge insulator.
List of Figures ⅤII
Chapter 1 Introduction
1.1 Background and Motivation 1
1.2 Organization of the thesis 2
References 5
Chapter 2 Basic Concepts of Thin Film Transistor
2.1 Introduction 6
2.2 Polysilicon Film Fabrication Method 6
2.2.1 Excimer Laser Crystallization 7
2.2.2 Metal Induce Lateral Crystallization 9
2.2.3 Sequential Lateral Solidification 10
2.2.4 Continuous Grain Silicon 11
2.3 9- Mask Process Flow of LTPS TFT 11
2.4 Parameter Determination 15
2.4.1 Determination of the threshold voltage 15
2.4.2 Determination of the subthreshold swing 15
2.4.3 Determination of the Field-effect Mobility 16
2.4.4 Determination of the Ion and Ioff 16
2.5 Measurement Technology 17
2.5.1 C-V Measurement 17
2.5.2 I-V Characteristics 17
2.5.3 Atomic Force Microscopy Analysis 18
2.5.4 Scanning Electron Microscopy (SEM) 18
2.5.5 Transmission Electron Microscopy 19
2.5.6 Focus Ion beam 19
2.5.7 Powder XRD 19
2.6 Summary 20
Chapter 3 Mechanical Strain Effect of Thin Film Transistor
3.1 Introduction 22
3.2 Strain effect on mono silicon 22
3.3 Experimental Procedure 24
3.4 Results and Discussions 28
3.4.1 On Current and mobility 28
3.4.2 Inter Grain orientation 29
3.5 Summary 39
References 40
Chapter 4 Bias Temperature Instability of LTPS Thin Film
Transistor
4.1 Introduction 42
4.2 Experiment Procedure 43
4.3 Positive bias temperature instability of LTPS TFT 44
4.4 Negative bias temperature instability of LTPS TFT 54
4.4.1 I-V Behavior in High Voltage stress 55
4.4.2 Result and discussion 56
4.4.3 R-D model 57
4.5 Summary 58
References 60
Chapter 5 Summary
5.1 Summary 63
5.2 Future Work 64
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chapter2
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chapter 3
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chapter 4
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