|
[1] J. Sun, M. Xu, Y. Ying, and F. C. Lee, “High Power Density, High Efficiency System Two-Stage Power Architecture for Laptop Computers,” in Proc. IEEE PESC conf., pp. 231-237, 2006. [2] Y. Ren, M. Xu, K. Yao, Y. Meng, F. C. Lee, and J. Guo, “Two-stage approach for 12 V VR,” in Proc. IEEE APEC Conf., vol. 2, pp. 1306-1312, 2004. [3] C. Buttay, H. Morel, B. Allard, P. Lefranc, and O. Brevet, “Model requirements for simulation of low-voltage MOSFET in automotive applications,” IEEE Trans. Power Electron., vol. 21, no. 3, pp. 613-624, May. 2006. [4] A. Castellazzi, Y. C. Gerstenmaier, R. Kraus, and G. K. M. Wachutka, “Reliability analysis and modeling of power MOSFETs in the 42-V-powernet,” IEEE Trans. Power Electron., vol. 21, no. 3, pp. 603-612, May. 2006. [5] R. Elferich, T. Lopez, and N. Koper, “Accurate behavioural modeling of power MOSFETs based on device measurements and FE-simulations,” in Proc. IEEE power electronics and applications, European conference, 2005. [6] Y. Ren, M. Xu, J. Zhou, and F. C. Lee, “Analytical loss model of power MOSFET,” IEEE Trans. Power Electron., vol. 21, no. 2, pp. 310-319, March. 2006. [7] Y. Xiao, H. Shah, T. P. Chow, and R. J. Gutmann, “Analytical modeling and experimental evaluation of interconnect parasitic inductance on MOSFET switching characteristics,” in Proc. IEEE APEC conf., pp. 516-521, 2004. [8] Y. Bai, Y. Meng, A. Q. Huang, and F. C. Lee, “A novel model for MOSFET switching loss calculation,” in Proc. IEEE IPEMC conf., vol. 3, pp. 1669-1672, 2004. [9] Y. Ren, M. Xu, F. C. Lee, and P. Xu, “The optimal bus voltage study for 12V two-stage VR based on an accurate analytical loss model,” in Proc. IEEE PESC conf., pp. 4319-4324, 2004. [10] K. S. Oh, “MOSFET basics,” Fairchid Semiconductor, Application Note, an9010, 2000. [11] J. Brown, G. Moxey, “Power MOSFET Basics:Understanding MOSFET characteristics associated with the figure of merit,” Vishay Siliconix, Application Note, an605, 2003. [12] J. Brown, “Power MOSFET Basics:Understanding Gate Charge and Using It To Assess Switching Performance,” Vishay Siliconix, Application Note, an608, 2004. [13] Infineon IPD09N03LA Datasheet, http://www.infineon.com/upload/Document/IPD09N03LA_Rev2.0_G.pdf [14] Y. Ren, “High frequency , high efficiency two-stage approach for future microprocessors,” Ph.D. thesis, Virginia Polytechnic Institute and State University, April 2005. [15] M. Pavier, A. Sawle, A. Woodworth, R. Monteiro, J. Chiu, and C. Blake, “High frequency DC:DC power conversion: the influence of package parasitics,” in Proc. IEEE APEC conf., vol. 2, pp. 699-704, 2003 [16] T. Lopez, T. Duerbaum, T. Tolle, R. Elferich, “ PCB layout inductance modeling based on a time domain measurement approach,” in Proc. IEEE APEC conf., vol. 3, pp. 1870-1876, 2004. [17] G. Nobauer, D. Ahlersr, J. Ruiz-Sevillanno, “A method to determine parasitic inductances in buck converter topologies” Infineon, Application Note, 2004. [18] R. Maimo-uni, H. Tranduc, P. Rossel, D. Allain, and M. Napieralska. “Spice model for TMOS power MOSFETs,” Motorola Seminconductor, Application Note, an1043, 2005. [19] R. Elferich, and T. Lopez, “Impact of gate voltage bias on reverse recovery losses of power MOSFET,” in Proc. IEEE APEC conf., pp. 1390-1395, 2006. [20] T. Tolle, T. Duerbaum, R. Elferich, “ De-embedding of reverse recovery losses in fast switching VRM applications,” in Proc. IEEE APEC conf., vol. 2, pp. 958-963, 2003. [21] Q. Zhao, and G. Stojcic, “Characterization of Cdv/dt induced power loss in synchronous buck dc-dc converters,” in Proc. IEEE APEC conf., vol. 1, pp. 292-297, 2004. [22] A. Elbanhawy, “The Making of the Perfect MOSFET,” in Proc. IEEE PESC conf., pp. 2443-2447, 2006. [23] A. D. Valdivieso, “A method to estimate the optimum components in a high current buck converter design,” Infineon, Application Note, 2004. [24] International Rectifier, IRF7811A Datasheet, http://www.irf.com/product-info/datasheets/data/irf7811a.pdf [25] L. Balogh, “Design and application guide for high speed MOSFET gate drive circuit,” Texas Instruments Power Supply Design Seminar SEM-1400, pp. 2/1-2/39, 2004. [26] Renesas HAT2168H Datasheet, http://documentation.renesas.com/eng/products/transistor/rej03g0046_hat2168h.pdf [27] Y. Gao, A. Q. Huang, and Y. Gao, “Trench power JFET with integrated junction barrier schottky diode,” in Proc. IEEE IAS conf., vol. 1, pp. 359-363, 2006. [28] G. Belverde, A. Magri, M. Melito, S. Musumeci, R. Pagano, and A. Raciti, “Efficiency improvement of synchronous buck converter by Integrated schottky diode in low-voltage MOSFETs,” in Proc. IEEE ISIE conf., vol. 2, pp. 429-434, 2005. [29] S. Ono, Y. Yamaguchi, N. Matsuda, A. Takano, M. Akiyama, Y. Kawaguchi, and A. Nakagawa. “High density MOSBD (UMOS with built-in trench schottky barrier diode) for synchronous buck converters,” in Proc. IEEE ISPSD conf., 2006. [30]National semiconductor LM276 Datasheet, http://cache.national.com/ds/LM/LM2725.pdf [31] Renesas HAT2165H Datasheet, http://documentation.renesas.com/eng/products/transistor/rej03g0004_hat2165h.pdf [32] Y. Kawaguchi, T. Kawano, H. Takei, S. Ono, and A. Nakagawa, “Multi Chip Module with Minimum Parasitic Inductance for New Generation Voltage Regulator,” in Proc. IEEE ISPSD conf., pp. 371-374, 2005. [33] F. Merienne, J. Roudet, J. L. Schanen, “ Switching disturbance due to source inductance for a power MOSFET: analysis and solutions,” in Proc. IEEE PESC conf., vol. 2, pp. 1743-1747, 1996. [34] B. Yang, and J. Zhang, “Effect and utilization of common source inductance in synchronous rectification,” in Proc. IEEE APEC conf., vol. 3, pp. 1407-1411, 2005. [35] W. Teulings, J. L. Schanen, and J. Roudet, “MOSFET switching behaviour under influence of PCB stray inductance,” in Proc. IEEE IAS conf., vol. 3, pp. 1449-1449, 1996
|