臺灣博碩士論文加值系統

對於N型矽基板上的金氧半電容而言，其飽和電流主要為電子電洞對在界面及空乏區的復合機制，但是對於P型矽基板上的金氧半電容而言， 其飽和電流受控於空乏區內電子電洞之產生與表面陷阱電荷，矽基板內缺陷，還有次氧化層。這些機制可藉由電致發光方式還有其對溫度之響應來作驗證。由於N型矽基板上的金氧半電容，電子電洞容易有復合效應，會有明顯的電致光效果，對於P型矽基板上的金氧半電容，電子電洞的產生對熱有相當明顯的響應。然而負電容的現象存在於N型矽基板上的金氧半電容，尤其在元件面積比較大，且偏壓在平帶電壓附近時候特別明顯，其原因大致上跟界面電荷之捕捉和釋放有關。 對於P型矽基板上的金氧半電容，當矽基板溫度升高，在飽和電流區域時，少數載子電子從矽基板流進氧化層，容易破壞矽基板和氧化層界面，軟性崩潰機率隨之增加。更仔細探討軟性崩潰增加的原因，乃在於當矽基板溫度升高時，正偏壓加在金氧半電容閘極，矽基板裡的少數載子的的量急遽增加，表面陷阱電荷也更加活躍，容易有穿刺效應產生(percolation effect)，而且氧化層上電壓增加甚大，落在氧化層上的電場亦增加，於是容易造成金氧半電容體崩潰，不堪使用。此為當矽基板溫度增加時，電壓有重新分佈的情形，這現象對於一定厚度的氧化層，具有相當程度之破壞能力。 最後我們成功展示於三吋矽晶圓上溫度之分佈，藉由具有超薄純二氧化矽介電層的P型矽基板金氧半電容的特殊溫度效應所達成,當溫度增加時,少數載子亦增加，大致上溫度增加10°C，少數載子量也增加一倍,而電流也增加一倍，響應非常敏感且快速。但是當二氧化矽層厚度若太大，則不適用於低電壓操作。我們也作了一些改良，在二氧化矽上增添一層氧化鉿，可適合於低電壓操作。操作電壓僅有0.5伏特，飽和電流對溫度有良好響應，每當溫度升高10°C，電流即加倍。在30~90°C範圍內，穩定操作達四小時,並無元件退化現象，表示元件之穩定度實已相當足夠。在超大型的積體電路裡面，相當具有整合使用之潛力。

For MOS (n) capacitors, the saturation current is mainly attributed to the electron-hole pair recombination mechanism. But for MOS (p) capacitors, the saturation current is mainly attributed to the electron-hole pair generation mechanism, and is also controlled by interface trap densities (Dit), bulk traps, and suboxide. It can be examined by the electroluminescent (EL) method and their temperature dependencies. For the MOS (n) capacitors, because of the recombination mechanism, the EL phenomenon is easily found. However, for MOS (p) capacitors, because of the generation mechanism, the temperature response can be found. Furthermore, negative capacitance is found on a certain portion of MOS (n) C-V curves. It is probably in connection with the charge trapped and de-trapped in the interface and the charges have different phases. As the device size increasing, the negative capacitance is more obvious. For MOS (p) capacitors, the probability of soft breakdown (SBD) increases with temperature when biased in the saturation current region under substrate injection. The increase in the probability of SBD follows from the fact that increasing the temperature increases both the number of minority carriers and Dit, when the positive substrate injection region is biased. The amount of electrons near SiO2/Si interface will cause the percolation phenomenon effect. Therefore, the number of charges across the silicon dioxide increases so the voltage drop across the oxide increases, and finally SBD occurs. It is regarded as that the voltage will rearrange. The voltage rearrangement effect will damage the oxide films with a certain oxide thickness. We successfully demonstrated the temperature distribution on the 3-inch Si wafer by the conventional MOS (p) capacitors with pure SiO2 dielectrics. But when the thickness of SiO2 films increases slightly, the temperature sensitivity will decrease. It is not suitable for the application under low voltage operation. To do some improvement, the MOS (p) capacitors with hafnium oxide (HfO2) film added on SiO2 were demonstrated as reliable temperature-detecting devices for the first time. The saturation current of MOS (p) capacitor with added HfO2 film is easy to saturate within 0.5 V. Each increase of 10 °C almost doubles the saturation current. These devices are reliable even though they had been electrically stressed at various temperatures (30~90°C) for 4 hours. They are potential to be integrated into the circuits as temperature detectors for ultra large scaled integration technology

Contents Abstract (in Chinese)…………………..…………..………………………I
Abstract (in English)……………………………….……………………..II Acknowledgement………………………………………..………..………IV
Contents……………………………......….......…………………………………V
Table captions…………..…………..………..………………………….…VIII
Figure Captions…............……………….……………………..…………….. IX
Chapter 1 Introduction……………………………………………….1 1.1The development of CMOS technology and its challenge…… ……………….. ...1 1.2 The concept of MOS capacitor system………………………………………. …...4 1.2.1 Energy band diagram for the MOS capacitor..…….……………….……..4 1.2.2 Modified C-V extraction by quantum-mechanism and theoretical I-V analysis………………………………………… 5 1.2.3 Charges in silicon dioxide……...……………………………………….....5 1.3 On chip temperature detection for devices with Si-based substrate and the application of high-k material………………………………..6 1.4 Summary…………………………………………………………….…………….7 Chapter 2 Characterization of the MOS capacitors grown on N- and P-type substrates with ultra-thin oxides…………….13 2.1 Introduction………………………………………………………………………13 2.2 Experiment……………………………………………………………………….15 2.3 C-V and I-V properties…………………………………………………………...16 2.4 Conduction mechanisms of MOS capacitors…………………………………….20 2.4.1 Generation and recombination current…………………………………..20
3.2 Experiment………………………………………………………….……………59 VI
2.4.2 Electroluminescent (EL) test…………………………………………….22 2.4.3 Temperature effect……………………………………………………….23 2.5 Some effects on MOS capacitors………………..……………………………… 25 2.6 Summary………………………………….………………………………………28 Chapter 3 Temperature-induced voltage drop rearrangement and its effect on oxide breakdown in MOS (p) capacitor structure……………...57 3.1 Introduction……………………………………………………………………... 57 3.3 Energy band diagrams under different substrate temperatures……………….….59 3.4 Breakdown analysis…………………………………………………………...….61 3.4.1 Time zero dielectrics breakdown (TZDB)…………………………..61 3.4.2 Breakdown statistics…………………………………….……………63 3.4.3 C-V behavior…………………………………………………………64 3.5 Summary……………………………………………………………………..…..65 Chapter 4 Enhancement of temperature sensitivity for MOS (p) tunneling temperature sensors by utilizing hafnium oxide (HfO2) film added on silicon dioxide (SiO2)…………………………76 4.1 Introduction……………………………………………………………………..76 4.2 Experiment………………………………………………………………..….....78 4.3 Temperature detection characterization…………………………………………80 4.3.1 Temperature sensor array application…..…………………………........80 4.3.2 Device characterization……………………………..…………..……...82 4.3.2.1 Energy band diagram discussion………………………….82 4.3.2.2 Analysis of temperature sensitivity……………………….83 4.3.2.3Current gain method……. ………………………………..85 4.3.2.4 Reliability test……………………………………………..86
VII
4.4 Summary………………………………………………………………………....87 Chapter 5 Conclusion and suggestion for future work………………………………..104 5.1 Conclusion in this work…………………………………………………104 5.2 Suggestion for future work………………………………………………106 References……………………………………...…………………………….108

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