臺灣博碩士論文加值系統

在60GHz附近，7 GHz的連續頻寬造就了超高速室內無線通訊的可能性。最近幾年來，許多操作於60GHz的重要電路已用CMOS製程製作完成，進而論證了低成本接收發器製作的可能。在60-GHz的系統中，除了前端電路和頻率合成器外，超高速的調變器與解調變器之研製亦是一項重要的議題。此論文呈現了一些應用於60GHz室內無線通訊系統的重要電路；其中包含了一個操作於60-GHz的除頻器和一個十億位元頻率鍵移接收發器。

一個60-GHz的注入鎖定除頻器已利用了0.13-μm CMOS製程製作完成。與並聯共振的方法相比，模擬結果顯示提出的功率匹配技巧可以增加15%的鎖定範圍。依據量測的結果，除頻器的自振頻率在30.4GHz，其在注入功率為3dBm的條件下可達到6GHz的鎖定範圍(10%)；此電路在1.2V的偏壓下有8.8mW的功率消耗。
接下來，在發射機的部份；我們提出了利用混波式架構和動態注入鎖定技巧達到十億位元的操作速度和良好的頻帶外突波壓制；由量測結果可知，發射器可達到380ps的切換時間和8dB的突波壓制增益。此電路利用了0.13-μm CMOS製程製作完成；且在1.8V的偏壓下有51mW的功率消耗。

最後，一個十億位元頻率鍵移接收機亦利用了0.13-μm CMOS製程製作完成。與LC-tank延遲單元比較，提出的注入鎖定單元解決了傳統正交解調器所會遇到的延遲控制問題。根據模擬的結果，此接收器有424mV/GHz的解調常數；且在1.2V的偏壓下有20mW的功率消耗。

The contiguous bandwidth of 7GHz around 60GHz enables the realization of the ultra high-speed indoor wireless communications. In the recent years, many critical circuits at 60GHz have been fabricated in the CMOS technology to demonstrate the possibility of the low cost transceiver implementation. In addition to the front-end circuit and the frequency synthesizer, the ultra high-speed modulator and demodulator are also of main concern in 60-GHz systems. This thesis presents a 60-GHz frequency divider and a Gb/s FSK transceiver for 60 GHz indoor wireless communications.

A 60-GHz injection-locked frequency divider is implemented in a 0.13-μm CMOS technology. Compared with the shunt-peaking version, the proposed power-matched technique improves the locking range by 15% based on the simulation results. The measurement results show that the free-running frequency of the divider is 30.4GHz and the total locking range is 6GHz (10%) at input power of 3dBm while consuming 8.8mW from a 1.2V power supply.

The proposed mixer-based BFSK transmitter with injection locking technique achieves both 1Gbps operation speed and good out-band spur reduction. Measured settling time and spur reduction gain of the transmitter are 380ps and 8dB respectively while consuming 51mW from a 1.8V power supply. This transmitter is fabricated in a 0.13-μm CMOS technology.

A Gb/s FSK receiver is realized in a 0.13-μm CMOS technology. In Comparison with the LC-tank delay cell, the proposed injection-locked cell solves the critical delay-control problem of the conventional quadrature demodulator. The simulated demodulation constant of the receiver is 424mV/GHz while consuming 21mW from a 1.2V power supply.

Acknowledgement i
Abstract iii
Contents v
List of Figures viii
List of Tables x

1. Introduction . . . . . . . . . . . . . . . . . . 1
1.1 Background . . . . . . . . . . . . . . . . . . 1
1.2 Motivation . . . . . . . . . . . . . . . . . . 3
1.3 Overview of thesis . . . . . . . . . . . . . . . 4
1.4 Reference . . . . . . . . . . . . . . . . . . . . . 5
2. A 60-GHz Frequency Divider in 0.13-μm CMOS Technology . . 6
2.1 Introduction . . . . . . . . . . . . . . . . . . . . 6
2.2 Design of the 60-GHz Frequency Divider . . . . . . . 8
2.2.1 Divider Topologies . . . . . . . . . . . . . . . . 8
2.2.2 Transmission Lines . . . . . . . . . . . . . . . 10
2.3 Experimental Results . . . . . . . . . . . . . . . 12
2.4 Summary . . . . . . . . . . . . . . . . . . . . . . 14
2.5 Reference . . . . . . . . . . . . . . . . . . . . 15
3. Analysis and Modeling of Injection-Locked Oscillator . . . 16
3.1 Introduction . . . . . . . . . . . . . . . . . . . 16
3.2 Adaptive Spur Reduction Technique . . . . . . . . 17
3.2.1 Gain and Linearity Trade-Off . . . . . . . . . . 17
3.2.2 Adaptive Spur Reduction Technique . . . . . . . . 18
3.2.3 Applications . . . . . . . . . . . . . . . . . . 21
3.3 Analysis of Injection-Locked Oscillator . . . . . . 22
3.3.1 Model of Injection-Locked Oscillator . . . . . . 22
3.3.2 Settling time Analysis . . . . . . . . . . . 23
3.3.3 Spur Reduction Analysis . . . . . . . . . . . . 27
3.4 Summary . . . . . . . . . . . . . . . . . . . . . 34
3.5 Reference . . . . . . . . . . . . . . . . . . . . 35
4. Gb/s FSK Transmitter in 0.13-μm CMOS Technology . . . 36
4.1 Introduction . . . . . . . . . . . . . . . . . . . 36
4.2 Transmitter Architecture . . . . . . . . . . . . . 37
4.2.1 General Architecture . . . . . . . . . . . . . 37
4.2.2 Mixer-based FSK Transmitter with Injection Locking Technique . . . 39
4.3 Design and Analysis of Building Blocks . . . . . . . 41
4.4 Experimental Results . . . . . . . . . . . . . . . . 52
4.5 Summary . . . . . . . . . . . . . . . . . . . . . . 56
4.6 Reference . . . . . . . . . . . . . . . . . . . . . 57
5. Gb/s FSK Receiver in 0.13-μm CMOS Technology . . . 58
5.1 Introduction . . . . . . . . . . . . . . . . . 58
5.2 Receiver Architecture . . . . . . . . . . . . . . 59
5.2.1 General Architecture . . . . . . . . . . . . . . 59
5.2.2 FSK Demodulator with Injection-Locked Cell . . . 60
5.3 Design and Analysis of Building Blocks . . . 63
5.4 Simulation Results . . . . . . . . . . . . . . . 67
5.5 Summary . . . . . . . . . . . . . . . . . . . . . 69
5.6 Reference . . . . . . . . . . . . . . . . . . . . 70
6. Conclusion . . . . . . . . . . . . . . . . . . . . 71

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