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研究生:余宇昕
研究生(外文):Yee-Sin Er
論文名稱:使用雙臨界電壓絕緣體上矽互補式金氧半技術及內容可定址記憶體記憶單元之cache電路設計
論文名稱(外文):A Cache Memory Using SOI DTMOS Technique and a Content-Addressable-Memory Cell Approach
指導教授:郭正邦郭正邦引用關係
指導教授(外文):James B. Kuo
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電機工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:中文
論文頁數:63
中文關鍵詞:雙臨界電壓記憶體
外文關鍵詞:Cache MemoryDTMOS
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在本論文中,描述新的Cache記憶體具有適合低功率、低電壓應用的電路和結構。
  在第二章將瀏覽基本Cache記憶體的原理,提出使用部分解離絕緣體上矽互補式金氧半動態臨界電壓技術擁有快速標籤比對能力的新型低電壓內容可定址記憶體記憶單元,其使用動態控制電晶體的基體電壓和雙臨界電壓的技術,以達到快速比對的能力。
在第三章將介紹Cache記憶體的的設計,其中包含了標籤部位和記憶體部位兩個部份。標籤部位含有標籤細胞、第二層解碼器、近似靜態的脈波產生器及標籤感應放大器。使用兩個雙輸入阜的記憶體於記憶體部位。最後是時序圖和討論Cache記憶體的運作方式。
1 導論

2 Cache記憶體
2.1 簡介
2.2 Cache記憶體的設計技術
2.2.1 完全聯結對映法(fully associative mapping)
2.2.2 直接對映法(direct mapping)
2.2.3 集合式聯結對映法(set-associative mapping)
2.2.4 表現評量
2.3 SOI CMOS Device
2.4 Dynamic Threshold Voltage CMOS Technique
2.5 SRAM Using Dual Threshold Voltage
2.6 結論

3 Set-Associative CMOS Cache Memory Using Wordline-Oriented Tag-Compare(WLOTC) Structure with the Content-Addressable-Memory(CAM) 13-Transistor Tag cell
3.1 簡介
3.2 Cache記憶體的設計
3.2.1 標籤部位(Tag portion)
3.2.1.1 標籤細胞(tag cell)
3.2.1.2 第二層解碼器(second-level decoder)
3.2.1.3 近似靜態的脈波產生器(Quasi-Static Pulse Generator)
3.2.1.4 標籤感應放大器(Tag sense amplifier)
3.2.2 兩個輸出入的記憶體部位(Two-Port memory portion)
3.3 時序圖(Timing Chart)
3.4 操作和討論

4 總結

參考文獻
決定性路徑的SPICE模擬程式
第二章
2.1 J.B.Kuo and J.H.Lou, “Low-Voltage CMOS VLSI Circuits,” New York:John Wiley,1999.
2.2 K.Dosaka, Y.Konishi, K.Hayano, K.Himukashi, A.Yamazaki, C.A.Hart, M.Kumanoya, H.Hamano, and T.Yoshihara, “A 100MHz 4Mb Cache DRAM with fast copy-back scheme,”ISSCC Digest of technical paper, pp.148-149,Feb. 1994
2.3 J.P.Singh, H.S.Stone, and D.F. Thiebaut, “A model of workloads and Its Use in Miss-Rate Prediction for fully Associative Caches,”IEEE Transacions on computers, vol.41,no.7,pp.811-825,July 1994
2.4 D.Stiliadis and A. Varma, “Selective Victim Caching: A Method to Improve the performance of direct-mapped Caches,”IEEE Transactions on computers, vol. 46, no. 5, pp. 603-610, May 1997.
2.5 H. Mizuno, N. Matsuzaki, K.Osaka, T.Shinbo, N.Ohki, H. Ishida, K.Ishibashi, and T. kure, “A 1-v,100MHz,10-mW cahce using a separated bit-line memory hierarchy Architecture and domino tag comparators,” IEEE Journal of Solid-State Circuits,vol.31, no.11,pp. 1618-1624, NOV.1996.
2.6 Vincent P. Heuring and Harry F. Jordan, “Computer Systems Design and Architecture”Addison Wesley,1997.
2.7 T euvo Kohonen, “Content-Addressable Memories”,Berlin; New York:Springer-Verlag, 1980
2.8 H. Kadota, J. Miyake, Y. Nishimichi, H.Kudoh, and K. Kagawa, “An 8-kbit content-addressable and reentrant memory,” IEEE J.Solid-State Circuits, vol. SC-20, pp.951-957, May1985.
2.9 S. C. Liu, F.A.WU,and J.B.kuo,”An Novel Low-voltage content-Addressable-Memory(CAM)cell with a fast tag-compare capability using partially depleted(PD)SOI CMOS dynamic-threshold(DTMOS)techniques”,IEEE J.Solid-State Circuits, vol.36,no.4,April 2001,pp.712-716.
2.10 Perng-Fei Lin and James B. Kuo, ” A 1-V 128-kb Four-Way Set-Associative CMOS Cache Memory Using Wordline-Oriented
Tag-Compare (WLOTC) Structure with the Content-Addressable-Memory
(CAM) 10-Transistor Tag Cell” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 4, APRIL 2001
2.10 Chua-Chin Wang, Po-Ming Lee, and Kuo-Long Chen, “An SRAM Design Using Dual Threshold Voltage Transistors and Low-Power Quenchers” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 10, OCTOBER 2003.

第三章
3.1 J.B.Kuo and J.H.Lou, “Low-Voltage CMOS VLSI Circuits,” New York:John Wiley,1999.
3.2 K.Dosaka, Y.Konishi, K.Hayano, K.Himukashi, A.Yamazaki, C.A.Hart, M.Kumanoya, H.Hamano, and T.Yoshihara, “A 100MHz 4Mb Cache DRAM with fast copy-back scheme,”ISSCC Digest of technical paper, pp.148-149,Feb. 1994
3.3 J.P.Singh, H.S.Stone, and D.F. Thiebaut, “A model of workloads and Its Use in Miss-Rate Prediction for fully Associative Caches,”IEEE Transacions on computers, vol.41,no.7,pp.811-825,July 1994
3.4 D.Stiliadis and A. Varma, “Selective Victim Caching: A Method to Improve the performance of direct-mapped Caches,”IEEE Transactions on computers, vol. 46, no. 5, pp. 603-610, May 1997.
3.5 H. Mizuno, N. Matsuzaki, K.Osaka, T.Shinbo, N.Ohki, H. Ishida, K.Ishibashi, and T. kure, “A 1-v,100MHz,10-mW cahce using a separated bit-line memory hierarchy Architecture and domino tag comparators,” IEEE Journal of Solid-State Circuits,vol.31, no.11,pp. 1618-1624, NOV.1996.
3.6 K.osada, H. Higuchi, K. Ishibashi, N.Hashimoto, and K. Shiozawa, “A 2-ns access 285-MHZ two-port cache marco using double global bitline pairs,”in ISSCC dig. of tech. papers,1997,pp.402-403
3.7 H. Kadota, J. Miyake, Y. Nishimichi, H.Kudoh, and K. Kagawa, “An 8-kbit content-addressable and reentrant memory,” IEEE J.Solid-State Circuits, vol. SC-20, pp.951-957, May1985.
3.8 Perng-Fei Lin and James B. Kuo, ” A 1-V 128-kb Four-Way Set-Associative CMOS Cache Memory Using Wordline-Oriented
Tag-Compare (WLOTC) Structure with the Content-Addressable-Memory
(CAM) 10-Transistor Tag Cell” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 4, APRIL 2001
3.9 Kuo, J.B.; Lin, P.F.; Wang, F.; Chang, H.H.; Wang, W.T.; Chen, C.H.,” A 1-V, 3.44-ns, 4.1-mW at 50-MHz, 128-Kb four-way set-associative CMOS cache memory implemented by 1.8V 0.18µm foundry CMOS technology for low-voltage low-power VLSI system applications” 26th European Solid-State Circuits Conference pp. 308-311 September 2000.
3.10 Chua-Chin Wang, Po-Ming Lee, and Kuo-Long Chen, “An SRAM Design Using Dual Threshold Voltage Transistors and Low-Power Quenchers” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 10, OCTOBER 2003.
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