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研究生:陳昭綸
研究生(外文):Chao-Lun Chen
論文名稱:JPEG-LS編碼器之交易層級模型及其驗證使用SystemC
論文名稱(外文):Transaction Level Modeling and Verification of JPEG-LS Encoder using SystemC
指導教授:王勝德王勝德引用關係
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電機工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:中文
論文頁數:43
中文關鍵詞:SystemCJPEG-LSTLM驗證編碼器
外文關鍵詞:SystemCJPEG-LSTLMVerificationencoder
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系統單晶片 (System on Chip,SoC) 設計隨著半導體製程的進步,其設計愈來愈複雜,系統設計者面臨更大的系統設計與硬體驗證的諸多挑戰。因此開始尋求可以處理複雜系統,並且能夠盡快將產品導入市場的方法。為了簡化晶片設計的流程,系統層級設計因此變的更加重要。
SystemC 2.0 提供交易層級模型 (Transaction Level Modeling) 一個方便的設計方式,讓設計者以更高階的視野來看待整個系統的設計,在設計的初期即可進行系統的驗證,避免系統設計到RTL (Register Transfer Level) 時才發現錯誤,減少設計的成本。
本論文以SystemC 2.0為基礎,呈現JPEG-LS交易層級模型的設計流程,從高階的演算法層級一直演進到RTL,在不同的模型之間說明設計的差異並進行驗證及效能的分析。
With the ever-increasing complexity of System-on-Chip, the designer faces great challenges to design a system. So the designer has been searching for new methodology that can handle the complexity with increased productivity and decreased time-to-market. In order to simplify the design flow of an application specific integrated circuit, the system level design issue is getting more important.
SystemC provides a convenient design flow for transaction level modeling and allow the designers create the design of the whole system on a high level stage, and verify the system at the early model, as well as down to the RTL model. Consequently, it can reduce the design cost. In this thesis we present the design flow of transaction level modeling of a JPEG-LS encoder based on SystemC from the algorithm level down to the register transfer level, and compare the diversity of different models. Finally, we verify the system design and performance analysis.
第一章 緒論 1
1.1 概述 1
1.2 研究動機 4
1.3 論文架構 5
第二章 JPEG-LS演算法 6
2.1 編碼概念 6
2.2 影像特性 7
2.3 詳細編碼流程 8
2.3.1 編碼架構 8
2.3.2 演算法 9
第三章 SystemC 概要 18
3.1 SystemC 設計流程 18
3.2 SystemC語言架構 19
3.3 模組 (Modules) 20
3.4 Interfaces和Ports 21
3.5 Processes和Events 22
3.6 資料型別 (Data types) 23
第四章 TLM設計 25
4.1 Specification model 26
4.1.1 定義 26
4.1.2 設計 26
4.2 Component-assembly model 27
4.2.1 定義 27
4.2.2 設計 27
4.3 Bus-arbitration model 28
4.3.1 定義 28
4.3.2 設計 28
4.4 Bus-functional model 29
4.4.1 定義 29
4.4.2 設計 30
4.5 Implementation model 30
4.5.1 定義 30
4.5.2 設計 30
4.6 驗證 (Verification) 32
4.6.1 基本驗證 32
4.6.2 SystemC Verification Standard 驗證方法 33
第五章 實驗結果與效能分析 35
5.1 測試環境 35
5.2 測試圖片 35
5.3 執行結果(1)–模擬時間 36
5.4 執行結果(2) – Clock cycle數 37
5.5 執行結果(3) – 改進系統架構 37
5.6 執行結果(4) – 縮減data line、資料寬度 39
第六章 結論 41
參考文獻 42
[1]R. Clark, “FCD 14495, Lossless and near-lossless coding of continuous tone still images (JPEG-LS),” Public Draft FCD 14495, ISO/IEC JTC1/SC29 WG1 (JPEG/JBIG), 1997.
[2]Open SystemC Initiative, ”SystemC”, http://www.systemc.org.
[3]縐永良, “SystemC語言概論,” CIC, Nov 2004.
[4]T. Grotker et al. System Design with SystemC. Kluwer, 2002.
[5]F. Ghenassia, TRANSACTION-LEVEL MODELING WITH SYSTEMC, Springer, 2005.
[6]Lukai Cai, Daniel Gajski, “Transaction Level Modeling: An Overview,” CODES+ISSS’03, 2003.
[7]D. C. Black and J. Donovan. SystemC: From the Ground Up. Kluwer Academic Publishers, 2004.
[8]D. D. Gajski and L. Cai, Transaction Level Modeling in System Level Design, Technical Report #03-10, March 28, 2003.
[9]C. Norris Ip and Stuart Swan, A Tutorial Introduction on the New SystemC Verification Standard, submitted for publication, September 2002.
[10]Stuart Swan, An Introduction to System Level Modeling in SystemC 2.0, white paper, www.SystemC.org.
[11]The SystemC Verification Standard, version 1.0, to appear at www.SystemC.org.
[12]R. Jindal, and K. Jain, Verification of transaction-Level SystemC models using RTL Testbenches, MEMPCPDE 2003, pp.199-203
[13]S. Pasricha. “Transaction Level Modelling of SoC with SystemC 2.0,” in Synopsys User Group Conference, 2002.
[14]D. Gajski et al. SpecC: Specification Language and Methodology. Kluwer, Jan 2000.
[15]L. Cai et al. Comparison of SpecC and SystemC languages for System Design. Technical Report CECS-TR-03-11, UCI, May 2003.
[16]S. Swan, SystemC Transaction Level Models And RTL Verification, Design Automation Conference, 2006 43rd ACM/IEEE 24-28, July, 2006. pp. 90–92.
[17]N. Calazans, E. Moreno, F. Hessel, V. Rosa, F. Moraes, and E. Carara, “From VHDL Register Transfer Level to SystemC Transaction Level Modeling: a Comparative Case Study,” Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings. 16th Symposium on 8-11 Sept. 2003. pp. 355–360.
[18]Synopsys Inc. SystemC Version 2.0 Users Guide. 2003. Available at: www.systemc.org
[19]D. Micheli, G. Gupta, “Hardware/software co-design,” Proceedings of the IEEE, 85(3), March, 1997. pp. 349-365.
[20]A. Donlin, “Transaction Level Modeling: Flows and Use Models,” Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, September 08-10, 2004, Stockholm, Sweden.
[21]M. Burton, A. Donlin, “Transaction Level Modeling: Above RTL design and methodology”, Open SystemC Initiative TLM-Working Group. http://www.systemc.org/
[22]MJ Weinberger, G Seroussi, G Sapiro, “The LOCO-I lossless image compression algorithm: principles andstandardization into JPEG-LS,” Image Processing, IEEE Transactions on, 2000 - ieeexplore.ieee.org
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