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研究生:邱顯嘉
研究生(外文):Hsien-Chia Chiu
論文名稱:摻雜對完全矽化鎳的製作專用於閘極矽化金屬材料在CMOS65奈米元件之影響
論文名稱(外文):Dopant Enhanced in Ni-FUSI Process for Sub-65nm CMOS Gate Electrode Application
指導教授:譚湘瑜
指導教授(外文):S.Y. Tan
學位類別:碩士
校院名稱:中國文化大學
系所名稱:材料科學與奈米科技研究所
學門:工程學門
學類:化學工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:中文
論文頁數:92
中文關鍵詞:矽化鎳離子佈植CMOS金屬閘極ISE-TCAD
外文關鍵詞:NiSiMetal GateCMOSIon implantationISE-TCAD
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當CMOS元件縮減到奈米尺寸的等級後,利用複晶矽(poly-Si)作為CMOS元件之閘極主要材料的技術已經到了一個瓶頸,因為高阻值及閘極空乏效應變成很大的問題,所以必須尋找新的材料來取代複晶矽,而使用金屬閘極,可能是唯一的解決辦法,金屬閘極有金屬的低電阻特性,而且不會產生空乏效應,但是因為金屬閘極仍然有許多問題,因此使用矽化鎳(NiSi)金屬矽化物閘極來取代金屬閘極。在本論文的第一部分,為了降低NiSi在高溫會產生薄膜結塊的現象,本論文利用了離子佈植及兩階段退火的方式來改善薄膜團縮結塊的現象,並且我們得到了當離子佈植後出現NiSi薄膜結塊的溫度延遲到775℃,而其中摻有氮(N+)離子的NiSi薄膜更可延遲到825℃,並且在775℃前皆可以維持低的片電阻值(2.5Ω/□以下),然而本實驗也發現掺入離子確實能提升薄膜穩定性。第二部份將利用ISE-TCAD半導體元件製程模擬軟體,藉由實驗所得的參數加入模擬中,將矽化鎳應用於65奈米的電晶體元件模擬,而我們得到摻雜了N+離子能夠得到最大驅動電流為364 mA/mm,同時也得知當不同的離子佈植後在65nm MOSFET所能夠得到不同的截止電壓Vth與最大轉導函數Gm及最大驅動電流Id,因此NiSi材料的確是適合被用在65nm CMOS元件上一個不可或缺的材料。
When CMOS device dimensions are scaled down sub-100 nm, poly-Si gate technology such as high resistance and gate depletion become problems. Using the metal as gate electrode material may be the only way to solve these problems. Metal gate material not only eliminates the gate depletion, but also greatly reduces the sheet resistance and contact resistance. First section, to reduce the defect of NiSi agglomeration at high temperature, a two-step anneal process and ion implantation have been used. In the paper, it shows that additional ion implantation can suppress the high temperature agglomeration of NiSi, and improve the thermal process window up to 775 °C. Then N+ ion implantation has best property can improve the thermal window up to 825 °C and it still obtains lower sheet resistance. Analysis techniques such as XRD, SEM, and four-point probe are carried out to demonstrate its physical and electrical properties. Finally, we use ISE-TCAD Semiconductor device simulation software to simulate the MOSFET device’s fundamental characteristic.
摘要 I
Abstract II
謝誌 III
目 錄 IV
圖目錄 VI
表目錄 IX
第一章 緒論 1
1.1、前言 1
1.2、金屬矽化物簡介 2
1.3、研究動機 3
1.4、論文架構 4
第二章、文獻回顧 6
2.1、金屬矽化物製程技術的發展 6
2.2、金屬矽化物製程 10
2.3、常用的金屬矽化物種類 14
2.4、常見的一些金屬矽化物問題 20
第三章、實驗設備 23
3.1、實驗步驟 26
3.2、分析方法說明 32
3.2.1、四點探針 32
3.2.2、X光繞射分析儀 34
3.2.3、掃描式電子顯微鏡 37
第四章、結果與討論 41
4.1、四點探針分析 41
4.2、XRD分析 45
4.3、SEM分析 52
第五章、利用ISE-TCAD針對不同NiSi功函數之元件模擬 62
5.1、ISE-TCAD軟體簡介 62
5.2、分析方法與物理模型 63
5.3、NiSi/SiO2/Si堆疊結構及材料參數設定 68
5.4、ISE-TCAD模擬結果與討論 69
第六章、總結 74
參考文獻 76
附錄 81
[1] H. Iwai et. al., “NiSi salicide technology for scaled CMOS,” Microelectronic vol. 60, p. 157. 2002. Engineering,
[2] T. Morimoto, H. S. Momose, T. Iinuma, I. Kunishima, K. Suguro, H. Okano, I Katakabe, H. Nakajima, M. Tsuchiaki, M. Ono, Y. Katsumata, H. Iwai, A NiSi salicide technology for advanced logic devices, IEDM Tech. Dig. (1991) 653–656.
[3] T. Ohguro, S. Nakamura, M. Koike, T. Morimoto, A. Nishiyama, Y. Ushiku, T. Yoshitomi, M. Ono, M. Saito, H. Iwai, Analysis of resistance behavior in Ti- and Ni-salicided polysilicon films, IEEE Trans. Electron Devices 41 (1994) 2305–2317.
[4] T. Ohguro, S. Nakamura, M. Saito, M. Ono, H. Harakawa, E. Morifuji, T. Yoshitomi, T. Morimoto, H. S. Momose, Y. Katsumata, H. Iwai, Ultra-shallow junction and salicide techniques for advanced CMOS devices, Proc. ESC Symp ULSI Sci. Technol., vol. PV-97-3 (1997) 275–295.
[5] J. C. Barbour, A. E. M. J. Fischer and J. F. van deer Veen, “The thin-film reaction between Ti and thermally grown SiO2”, J. Appl. Phys., vol. 62, pp.2582, 1987.
[6] J.P.Gambinoa, E.G. Colgan, “Invited Review Silicide and ohmic contacts”, p.99-146 (1998)
[7] G. J. van Grup, W. F. van der Weg, and D. Sigurd, “interaction in theCo/Si Thin Film System. Ⅱ. Diffusion Maker Experimenrts”, J. Appl.Phys. 49 (1978) 4011-4020
[8] 莊達人,"VLSI製造技術", 高立圖書, 1994.
[9] J. C. Barbour, A. E. M. J. Fischer and J. F. van deer Veen, “The thin- film reaction between Ti and thermally grown SiO2,” J. Appl. Phys., vol. 62, pp.2582, 1987.
[10] T. Ohguro et al., IEEE Tran. Electron Devices, ED-41, p.2305 (1994).
[11] G. T. Sarcona, M. Stewart, M.K. Hatalis, “Polysilicon thin-film transistors using self-aligned cobalt and nickel silicide source and drain contacts” , IEEE Electron Device Letters, vol. 20, Issue: 7, pp. 332, 1999.
[12] W.T. Sun, M.C. Liaw, “Suppression of cobalt silicide agglomeration using nitrogen(N2+) implantation” , IEEE Electron Device Letters, vol. 19, pp. 163, 1998.
[13] S. R. Das, D. X. Xu, M. Nournia, L. Lebrun, A. Naem, “Thermal Stability of nickel silicide films” , Mat. Res. Soc. Symp. Proc. , vol. 427, pp. 541, 1996.
[14] M. C. Poon, F. Deng, M. Chan, W. Y. Chan, S. S. Lau, “Resistivity and thermal stability of nickel mono-silicide” , Applied Surface Science, vol. 157, pp. 29, 2000.
[15] M. C. Poon, M. Chan, W. Q. Zhang, F. Deng, S. S. Lau, “Stability of NiSi in boron-doped polycilicon lines,” Microelectronics Reliability, vol. 38, pp. 1499, 1998
[16] T. Ohguro et al., Proc. SSDM, p.192 (1993).
[17] J. B. Lasky, J. S. Nakos, D. J. Cain, andP. J. Geiss, “Comparison of Transformation to Low-Resistivity Phase and Aggeramation of TiSi2 and C0Si2”, IEEE Tran. Electron. Devices, ED-38, p.262-269 (1991)
[18] 吳泰伯、許樹恩,“X光繞射原理與材料結構分析”,中國材料科學學會 (1996)。
[19] 汪建民,“材料分析”,中國材料科學學會 (1998)。
[20] 陳力俊等,”材料電子顯微鏡學”,國科會精儀中心 (1997)。
[21] M. Qin, V. Poon, and S. Ho, “Investigation of polycrystalline nickel silicide films as a gate material," Journal of the Electrochemical Society, vol. 148, no. 5, pp. G271-4, 2001.
[22] W. Maszara, Z. Krivokapic, P. King, J.-S. Goo, and M.-R. Lin, “Transistors with dual work function metal gates by single full silicidation (FUSI) of polysilicon gates," in International Electron Devices Meeting. Technical Digest, Dec. 2002, pp. 367-70.
[23] J. Sim, H. Wen, J. Lu, and D. Kwong, “Dual work function metal gates using full nickel silicidation of doped poly-si,” IEEE Electron Device Letters, vol. 24, pp. 631{3, Oct. 2003.
[24] J. Kedzierski, D. Boyd, C. J. Cabral, P. Ronsheim, S. Zafar, P. Kozlowski, J. Ott, and M. Ieong, “Threshold voltage control in NiSi-gated MOSFETs through SIIS," IEEE Transactions on Electron Devices, vol. 52, pp. 39-46, Jan. 2005
[25] D. Aime, B. Froment, F. Cacho, V. Carron, S. Descombes, Y. Morand, N. Emonet, F. Wacquant, T. Farjot, S. Jullian, C. Laviron, M. Juhel, R. Pantel, R. Molins, D. Delille, A. Halimaoui, D. Bensahel, and A. Souifi, “Work function tuning through dopant scanning and related effects in Ni fully silicided gate for sub-45nm nodes CMOS,” in International Electron Devices Meeting. Technical Digest, Dec. 2004, pp. 87-90.
[26]1995–2004 ISE Integrated Systems Engineering AG, ISE TCAD Release 10.0,使用手冊
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