臺灣博碩士論文加值系統

傳統的直接數位頻率合成器（Direct Digital Frequency Synthesizer）作為時脈產生器時，通常存在有相位抖動的問題。為了改善這個相位抖動的問題，在本論文中我們提出了一個新的相位運作式直接數位頻率合成器，它利用相位累加器（Phase Accumulator）的輸出在第一階段於單一積分電容上做正斜率積分，而在第二階段時，則使用頻率設定值於相同的積分電容上做負斜率積分。所以透過在同一電容上使用雙斜率積分（Dual-slope integration），將可以避免電容值的誤差，因此能產生一個較準確的校正延遲時間；進而獲得低抖動（Low-jitter）的時脈輸出。
在硬體實現方面，本篇論文採用陳信全博士所提出之”雙斜率積分式直接數位頻率合成器（Direct Digital Frequency Synthesizer, DLSP-DDS）”為主體架構，並且使用硬體描述語言（Very High Speed ICs Hardware Description Language, VHDL）去設計，並配合一些相關類比元件實現此一DDS架構。

There exists a phase jitter problem in using the conventional DDS as a pulse or clock generator. In this paper, a new phase-interpolation DDS scheme is proposed, which uses the output of the phase accumulator to provide positive-slope integration on an integration capacitor in the first phase, and then performs negative-slope integration operation on the same integration capacitor in the second phase. By using dual-slope integration on a single capacitor, the capacitance value error can be avoided and less chip size can be used in circuit implementation. Therefore, the proposed DDS can achieve a low-jitter clock output due to generating the more precise delay time.
In the hardware for achieve, The structure of this page thesis adopts ”Direct Digital Frequency Synthesizer” for Dr.Chen puts forward, and use “Very High Speed ICs Hardware Description Language, VHDL” to be designed, and cooperate with some relevant analog components and achieve this DDFS structure.

第一章 緒論1-1 DDS(Direct Digital Frequency Synthesizer)概述
1-2 研究動機
1-3 論文規劃
第二章 頻率合成器（Frequency Synthesizers）
2-1 頻率合成器概述
2-2 傳統頻率振盪
2-2.1 基本回授振盪電路
2-3 鎖相迴路
2-3.1 參考頻率fr對迴路的影響
2-4 直接數位式頻率合成器(Direct Digital Frequency Synthesizer, DDS)
2-4.1 傳統DDS(唯讀記憶查表法)概述
2-4.2 雙電容積分方式DDS
第三章 雙斜率積分方式之低抖動相位運作式直接數位頻率合成器(Low jitter Phase interpolation Direct Digital Frequency Synthesizer using Dual Slope integration, DLSP-DDS)
3-1 DLSP-DDS概述
3-2 基本原理
3-3 動作時序
3-4 時間延遲誤差
第四章 硬體實現
4-1 硬體實現概述
4-2 實驗板(EP1K100QC208)規格介紹
4-3 DLSP-DDS硬體實現
4-3.1 累加電路
4-3.1.1軟體模擬與實際量測結果
4-3.2 除頻電路
4-3.2.1軟體模擬與實際量測結果
4-3.3 控制電路
4-3.3.1 軟體模擬與實際量測結果
4-4.4 延遲產生器
4-4.5 比較器與T-FF電路
4-4.6 整合電路後DLSP-DDS的量測結果
第五章 結論

[1] G. Puccio, “Layout design of a direct digital frequency synthesizer as a frequency dehopper for a spread spectrum communication system on sea-of-gates,” Master's Thesis, Delft University of Technology, Faculty of Electrical Engineering, Electronic Engineering Group, the Netherlands, pp. 94-A6, July 1994.
[2] D. E. Calbaza and Y. Savaria, “Direct digital frequency synthesis of low-jitter clocks,” in Proc. IEEE 2000 Custom Integration Circuits Conference, pp. 31-34, 2000.
[3] 賈證主, “VHDL數位系統設計與應用”, 台科大圖書股份有限公司, 台北縣 2004年11月
[4] Rokita, A., “Direct analog synthesis modules for an X-band frequency source,” MIKON '98, 12th International Conference on Microwaves and Radar, on 20-22 May 1998, Page(s):63 - 68, vol.1.
[5] Sheen, R.R.-B., Chen, O.T.-C., Chang, R.C.-H., “A 1.3 V 1.04 GHz-1.30 GHz CMOS phase-locked loop,” Proceedings of the 40th Midwest Symposium on Circuits and Systems, 1997, on Volume 1, 3-6 Aug. 1997, Page(s):569 - 572.
[6] Sheen, R.R.-B., Chen, O.T.-C., “A 3.3 V 600 MHz-1.30 GHz CMOS phase-locked loop for clock synchronization of optical chip-to-chip interconnects,” Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, 1998. ISCAS '98, Volume 4, 31 May-3 June 1998 Page(s):429 - 432.
35
[7] De Caro, D., Strollo, A.G.M., “High-Performance Direct Digital Frequency Synthesizers Using Piecewise-Polynomial Approximation,” IEEE Transactions on Circuits and Systems I: Regular Papers, on see also Circuits and Systems I: Fundamental Theory and Applications, on Volume 52, Issue 2, Feb. 2005.
[8] Bellaouar, A., O'brecht, M.S., Fahim, A.M., Elmasry, M.I., “Low-power direct digital frequency synthesis for wireless communications,” IEEE Journal of Solid-State Circuits, Volume 35, Issue 3, March 2000.
[9] Jen-Chuan Chih, Jun-Yei Chou, Sau-Gee Chen, “An efficient direct digital frequency synthesizer based on two-level table lookup,” Proceedings of the 2001 IEEE International Frequency Control Symposium and PDA Exhibition, 2001, 6-8 June 2001 Page(s):824 - 827.
[10] Eltawil, A.M., Daneshrad, B., “Interpolation based direct digital frequency synthesis for wireless communications,” 2002 IEEE Wireless Communications and Networking Conference. WCNC 2002, on Volume 1, 17-21 March 2002.
[10]Byung-Do Yang, Choi, J.-H., Seon-Ho Han, Lee-Sup Kim, Hyun-Kyu Yu, “An 800-MHz low-power direct digitynthesizeral frequency s with an on-chip D/A converter,” IEEE Journal of Solid-State Circuits, on Volume 39, Issue 5, May 2004.
[11]袁杰, “實用無線電設計”, 全華科技圖書股份有限公司, 台北市2003
36
[12]H. Nosaka, Y. Yamaguchi, and M. Muraguchi, “A non-binary direct digital synthesizer with extended phase accumulator,” IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, vol. 48, no. 1, pp. 293-298, January 2001.