跳到主要內容

臺灣博碩士論文加值系統

(18.205.192.201) 您好!臺灣時間:2021/08/05 09:38
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

: 
twitterline
研究生:陳美利
研究生(外文):Mei-Li Chen
論文名稱:雙閘極金氧半場效電晶體小幾何行為之研究
論文名稱(外文):Investigation of Small-Geometrical Behavior on Double-Gate MOSFETs
指導教授:江德光
指導教授(外文):Te-Kuang Chiang
學位類別:博士
校院名稱:南台科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:英文
論文頁數:144
中文關鍵詞:短通道效應汲極偏壓導致通道電位屏障降低之效應次臨界電流量子局限長度邊緣導致能帶下降效應雙閘極金氧半場效應電晶體特徵長度臨界電壓次臨界電流隨著閘極電壓之改變率短通道臨界電壓衰變量子效應載子局限效應雙材質閘極金氧半場效應電晶體
外文關鍵詞:Short-channel effectsQuantum mechanical effectsCarrier confinementDual-material double-gate MOSFETSubthreshold swingThreshold voltage degradationDrain-Induced Barrier LoweringSubthreshold currentDouble-gate MOSFETCharacteristic lengthFringing-induced barrier loweringQuantum confinement length
相關次數:
  • 被引用被引用:0
  • 點閱點閱:377
  • 評分評分:
  • 下載下載:48
  • 收藏至我的研究室書目清單書目收藏:0
未來的超大型積體電路元件研究設計發展趨勢已逐漸步入小幾何元件,甚至已達到奈米(Nanometer)層級;為了能夠預測超大型積體電路之電路表現,發展一個或一系列能精確預測與分析元件特性之模型已是刻不容緩的事。
近年來有關金氧半場效電晶體(Metal-Oxide-Semiconductor Field-Effect Transistor) (MOSFET) 的新幾何結構與新材料等陸續被提出而且備受矚目,對於未來的超大型積體電路元件研究設計而言;對稱型雙閘極(symmetrical double-gate) (SDG) 因其具有以下的優點:有效抑制短通道效應、低功率消耗、傑出的閘極通道控制能力、有效抑制邊緣電場導致通道電位能屏障(Fringing-Induced Barrier Lowering effect) (FIBL)下降效應、理想的次臨界電流隨著閘極電壓之改變率(subthreshold swing)值、高的導通電流(Ion)與高的轉移電導(transconductance)等。但是在元件步入深次微米領域時,最明顯的短通道效應(short-channel effects) (SCEs)即為“汲極偏壓導致通道電位屏障降低之效應"(Drain-Induced Barrier Lowering effect) (DIBL),因為此效應之產生,足以引發原先處於完全截止態之元件,再次導通;因而產生不需要之通道漏電流(channel leakage current),此漏電流將產生額外之功率消耗,並影響電路之穩定性。另外,隨著元件尺寸之急劇縮小,除了汲極偏壓導致通道電位屏障降低之效應(DIBL)之外,臨界電壓衰變(threshold voltage degradation)亦是構成短通道元件不易控制的重要因素,而且元件的次臨界電流隨著閘極電壓之改變率(subthreshold swing)值亦有明顯之改變;極少的閘極電壓變化,足以產生大量之次臨界電流,進而影響電路之功能。因此,分析及研究汲極偏壓導致通道電位屏障降低之效應(DIBL)、臨界電壓衰變(threshold voltage degradation)、以及次臨界電流隨著閘極電壓之改變率(subthreshold swing)值在深次微米元件中顯得格外重要。
另外,在元件達到奈米層級時;原先傳統電位輪廓可假設為一拋物線狀,並用以推導最小可接受縮減長度(scaling length),但由於量子效應(Quantum mechanical effects) (QM effects)所導致之載子局限(carrier confinement)現象,造成此假設已不再適用。對以矽材質為基體以及完全空乏(fully depleted)且具二氧化矽絕緣層結構的金氧半場效應電晶體而言,量子局限效應於閘極至氧化層間產生無限深之電位井。此電位井則是被上下兩個閘極的氧化層電位屏障所定義,且深受矽主體中電場之影響。當元件尺寸進入深次微米或甚至更低尺度時,藉由考慮量子局限效應,希望可以提供該元件更精確的次臨界行為解析模型。
本論文主要研究主題針對對稱型雙閘極金氧半場效電晶體做一系列的元件特性模型分析;本論文之第一章內容首先對金氧半場效電晶體做一回顧並指出未來的超大型積體電路元件研究設計發展趨勢已逐漸步入小幾何元件,甚至已達到奈米層級;因此列舉說明在元件步入深次微米領域時,基本的短通道效應(short-channel effects) (SCEs)行為;以及針對本論文將要探討研究的主體架構作概略說明。本論文之第二章中,首先分析傳統型對稱型雙閘極金氧半場效電晶體,其中包含矽基體與閘極絕緣層的帕森方程式完全解,精確推導出包含矽基體及閘極絕緣層的靜電位分佈(electrostatic potential)、短通道臨界電壓衰變(threshold voltage degradation)、次臨界電流(subthreshold current)、次臨界電流隨著閘極電壓之改變率(subthreshold swing)值、與汲極偏壓導致通道電位屏障降低效應(DIBL)。本論文之第三章接著探討當閘極介電層(Gate Dielectrics)厚度變小時所導致直接穿隧效應(Direct tunneling effect)進而促使閘極的漏電流增加,使得晶片靜態功率損失增大,影響元件之短通道性能(short channel performance)。因此分析以其他高介電係數(High-K)材料來取代傳統二氧化矽(SiO2)以改善直接穿隧效應;並精確推導出包含矽基體及含高介電係數材料閘極絕緣層的靜電位分佈(electrostatic potential)、含高介電係數材料短通道臨界電壓衰變(threshold voltage degradation)、含高介電係數材料之特徵長度(characteristic length)、並且與變分法之結果作一比較。
另外,新型結構研究也是本論文探討主題之一;本論文之第四章主要分析對稱型雙材質雙閘極金氧半場效電晶體(symmetrical dual-material double-gate MOSFET)(SDMDG MOSFET);首先由帕森方程式(Poisson’s equation)的二維完全解,推導出一系列全新與連續之有關雙材質對稱型雙閘極金氧半場效應電晶體之次臨界行為的解析式;本章精確推導出在不同雙材質閘極區域下的矽基體層的靜電位分佈(electrostatic potential)、通道臨界電壓(threshold voltage),以及因為汲極偏壓導致通道電位屏障降低效應(DIBL effect)而造成之通道臨界電壓衰變(threshold voltage degradation)、並且探討在通道總長度固定之下,改變不同閘極區域下的通道長度之短通道臨界電壓衰變(threshold voltage degradation),以及次臨界電流隨著閘極電壓之改變率(subthreshold swing)值。
本論文之第五章主要針對考慮量子效應對對稱型雙閘極金氧半場效電晶體產生之影響,亦即完整考量包括垂直於矽與二氧化矽介面之能量狀態的量化現象與能帶分裂結構,以期推導出對稱型雙閘極金氧半場效應電晶體應用於大型積體電路中之精確次臨界行為解析模型。本章中藉由一維的帕森方程式(Poisson equation)及薛丁格方程式(Schrodinger equation),以及利用在矽基體層與閘極介電層的界面之處必須滿足電通量連續的條件下;推導出在矽基體層的靜電位分佈(electrostatic potential)、以及由於量子效應(QM effects)而造成之通道臨界電壓衰變(threshold voltage degradation)。另外,傳統電位輪廓可假設為一拋物線狀,用以推導最小可接受縮減長度(scaling length),但由於量子效應(QM effects)所導致之載子局限(carrier confinement)現象,此假設已不再適用。因此本章中也推導出由於量子效應造成的量子局限長度(Quantum confinement length) λQM的解析式。
另外,我們進一步藉由元件模擬器之驗證,證實本論文之所有完整之解析方程式可以適用於對稱型雙閘極金氧半場效應電晶體。本論文之所有完整之解析方程式不僅提供對稱型雙閘極金氧半場效應電晶體元件特性之物理解釋,並且基於有效之演算,可以被應用於電路模擬器中之元件模型建立,且符合積體電路模擬與設計需求。
最後,在第六章中將說明本論文對於未來工作之展望。
As CMOS devices have been scaled down, the channel length shrinks and the absolute value of threshold voltage becomes smaller due to the reduced controllability of the gate over depletion region by the increased charge-sharing from the source/drain. Therefore, the study of short-channel effects (SCEs) have assumed a significant role because both the threshold voltage roll-off at decreasing gate length as well as drain-induced barrier lowering (DIBL) at increasing drain voltage pose a serious challenge to the efforts for down-scaling the CMOS technology. Double-Gate (DG) MOSFETs seem to be a very promising option for ultimate scaling of CMOS technology. In this dissertation, a physical and analytical model is developed for short-channel effects (SCEs) in fully depleted double-gate (DG) MOSFETs. On the base of resultant solution for 2-D Poisson’s equation included in both silicon film and gate oxide regions, the physical and analytical model including threshold voltage, subthreshold swing, and 2-D electrostatic potential for the short-channel fully depleted symmetrical double-gate (SDG) MOSFETs is developed. These analytical results can be used to model of DG MOSFET’s. The results calculated by the model agree well with the simulation data without any fitting parameters. They are also extendable to high-k gate insulators for precisely predicting the fringing field effects with high-k gate dielectrics.
To enhance the immunity against SCEs, a new structure called the dual-material gate (DMG) MOSFET has been proposed. In the DMG MOSFET, the work function of metal gate 1 (M1) is greater than metal gate 2 (M2) i.e., > and hence, threshold voltage > which has the inherent advantage of improving the gate transport efficiency by modifying the electric field pattern and the surface potential along the channel. Based on fully resultant 2-D potential solution, the physical and precisely analytical model for the short-channel fully depleted symmetrical dual-material double-gate (SDMDG) MOSFETs is successfully developed. The simulated results of the analytical model match well with those simulated by device simulator. Besides giving deep insight into the device physics, the analytical results are useful in compact modeling the threshold voltage of short-channel SDMDG MOSFET.
As the channel lengths of MOSFETs push into the nanometer regime, short-channel effects (SCEs) become intensively significant and put a hard limit to MOSFET performance. The design of optimal DG devices will require new insights into the underlying physics, especially the quantum mechanics (QM) of the carriers confined in very thin (tsi ≦10 nm) Si films. Quantum-mechanical confinement of inversion-layer carriers significantly affects the threshold voltage and gate capacitance of highly scaled MOSFETs. In this dissertation, we present a physical threshold voltage model in subthreshold region, and use analytical solutions to give design insight regarding the quantum effects in symmetrical DG MOSFETs. Quantization effects on DG MOSFET scalability is also examined in the thesis. This thesis not only provides a simple and computation-efficient short-channel surface potential and threshold voltage analytical model, but also offers the basic designing guideline for fully-depleted DG MOSFET.
摘要 i
Abstract iv
Acknowledgements vi
Contents vii
List of Table ix
List of Figures x
Chapter 1 Introduction 1
1.1 CMOS Overview and Transistor Scaling 1
1.2 Short-Channel Effects 6
1.2.1 Overview 6
1.2.2 Analytic Description of SCEs 8
1.3 Thesis Organization 13
Chapter 2 Two-Dimensional Analytical Model for Short-Channel Symmetrical
Double-Gate MOSFETs 16
2.1 Introduction 16
2.2 Model Derivation 18
2.2.1 Two-Dimensional Potential Analysis 18
2.2.2 The Threshold Voltage Analysis 30
2.2.3 The Subthreshold Swing Analysis 44
2.2.4 The Subthreshold Current Analysis 51
2.3 Conclusions 55
Chapter 3 Two-Dimensional Analytical Threshold Voltage Model for Symmetrical
Double-Gate MOSFETs with High-K Gate Dielectrics 56
3.1 Introduction 56
3.1.1 Issues of High-k Material and FIBL Effect 56
3.1.2 The Motive of this Thesis 61
3.2 Model Derivation 63
3.2.1 Two-Dimensional Potential Analysis 63
3.2.2 The Threshold Voltage Analysis 70
3.3 Conclusions 84
Chapter 4 Two-Dimensional Analytical Model for Short-Channel Symmetrical
Dual-Material Double-Gate MOSFETs 85
4.1 Introduction 85
4.2 Model Derivation 88
4.2.1 Two-Dimensional Potential analysis 88
4.2.2 The Threshold Voltage Analysis 100
4.3 Conclusions 110
Chapter 5 Quantum Mechanical Threshold Voltage Model for Short-Channel Symmetrical Double-Gate MOSFETs 111
5.1 Introduction 111
5.2 Model Derivation 113
5.2.1 Two-Dimensional Potential analysis 113
5.2.2 Quantum Mechanical Effects on Scalibility 124
5.3 Conclusions 128
Chapter 6 Conclusions and Future works 129
6.1 Conclusions 129
6.2 Future works 132
References 133
Publications List 144
[1.1] J. E. Lilienfeld, “Method and apparatus for controlling electric currents,” U.S. Patent, 1930.
[1.2] D. Kahng and M. M. Atalla, “Silicon–silicon dioxide field induced surface devices,” presented at the IRE Solid-State Device Res. Conf., Pittsburgh, PA, June 1960.
[1.3] X. Liang, “Analytical modeling of short channel effects in double gate MOSFET,” Ph. D Thesis, University of California, San Diego, 2006.
[1.4] R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous, and A. R. LeBlanc, “Design of ion-implanted MOSFETs with very small physical dimensions,” IEEE J. Solid-State Circuits, vol. SC-9, pp. 256–268, Oct., 1974.
[1.5] D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H.-S. P. Wong, “Device scaling limits of Si MOSFETs and their application dependencies,” IEEE Electron Device Lett., vol. 19, pp. 385–387, Oct., 1998.
[1.6] F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa, “Double gate
silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance”, IEEE Electron Device Lett., vol. EDL-8, pp.410-412, 1987.
[1.7] D. J. Frank, S. E. Laux, and M. V. Fischetti,“Monte Carlo simulation of a 30-nm double-gate MOSFET: How far can silicon go?"in IEDM Tech. Dig., pp.553-556, 1992.
[1.8] H.-S. P. Wong, D. J. Frank, Y. Taur, and J. M. C. Stork, “Design and performance considerations for sub-0.1 μm double-gate SOI MOSFETs,” in IEDM Tech. Dig., pp.747-750, 1994.
[1.9] H.-S. P. Wong, D. J. Frank, and P. M. Solomon, “Device design considerations for double-gate, ground-plain, and single-gated ultra-thin SOI MOSFETs at the 25 nm channel length generation,” IEDM Tech. Dig., pp. 407-410, 1998.
[1.10] R. H. Yan, A. Ourmazed, and K. F. Lee, “Scaling the Si MOSFET ﹕From bulk to SOI to bulk,"IEEE Trans. Electron Devices, vol.39 , pp.1704-1710, July, 1992.
[1.11] K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, and Y. Arimoto, “Scaling theory for double-gate SOI MOSFETs,"IEEE Trans. Electron Devices, vol.40, pp.2326-2329, December ,1993.
[1.12] J. C. S. Woo, K. W. Terrill and P. K. Vasudev, “Two-dimensional analytic modeling of very thin SOI MOSFET’s,” IEEE Trans. Electron Devices, vol. 37, pp.1999-2006, September, 1990.
[1.13] MEDICI. Two-dimensional device simulation program, Synopsys, 2003.
[1.14] T. N. Nguyen, “Small-geometry MOS transistors: Physics and modeling of surface- and buried-channel MOSFET’s,” Ph.D. dissertation, Stanford Univ., Stanford, CA, Tech. Rep. G545-2, 1984.
[1.15] D. J. Frank, Y. Taur, and H.-S. P. Wong, “Generalized scale length for two dimensional effects in MOSFETs,” IEEE Electron Device Lett., vol. 19, pp. 385-387, Oct., 1998.
[2.1] F. Balestra, S. Cristoloveanu, M. Benahir, J. Brini, and T. Elewa,“Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance,"IEEE Electron Device Lett., vol.8, pp.410-412, 1987.
[2.2] D. J. Frank, S. E. Laux, and M. V. Fischetti,“Monte Carlo simulation of a 30-nm double-gate MOSFET: How far can silicon go?"in IEDM Tech. Dig., pp.553-556, 1992.
[2.3] H. -S. P. Wong, D. J. Frank, and P.M. Solomon,“Device design considerations for double-gate, ground-plain, and single-gated ultrathin SOI MOSFETs at the 25 nm channel length generation,"in IEDM Tech. Dig., pp.407-410, 1998,.
[2.4] H. -S. P. Wong, D. J. Frank, Y. Taur, and J. M. C. Stork,“Design and performance considerations for sub-0.1μm double-gate SOI MOSFETs,"in IEDM Tech. Dig., pp.747-750, 1994,.
[2.5] K. Suzuki, Y. Tosaka, and T. Sugii,“Analytical threshold voltage model for short channel n+-p+ double-gate SOI MOSFETs,"IEEE Trans. Electron Devices, vol.43, pp.732-738, May, 1996.
[2.6] K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, and Y. Arimoto, “Scaling theory for double-gate SOI MOSFETs,"IEEE Trans. Electron Devices, vol.40, pp.2326-2329, December ,1993.
[2.7] K. Suzuki,"Short channel Epi-MOSFET Model,“IEEE Trans. Electron Devices, vol.47, pp.2372-2378, Dec., 2000.
[2.8] S. S. Chen and J. B. Kuo,“Deep submicrometer double-gate fully-depleted SOI pMOS Devices﹕A concise short-channel effect threshold voltage model using a quasi-2D approach,"IEEE Trans. Electron Devices, vol.43, pp.1387-1393, Sept., 1996.
[2.9] K. Suzuki, Y. Tosaka, and T. Sugii,“Analytical threshold voltage model for short channel double-gate SOI MOSFETs,"IEEE Trans. Electron Devices, vol.43, pp.1166-1168, July, 1996.
[2.10] Y. Tosaka, K. Suzuki, and T. Sugii,“Scaling-parameter-dependent model for subthreshold swing S in double-gate SOI MOSFETs,"IEEE Electron Device Lett., vol.15, pp.466-468, Nov., 1994.
[2.11] R. H. Yan, A. Ourmazed, and K. F. Lee, “Scaling the Si MOSFET ﹕From bulk to SOI to bulk,"IEEE Trans. Electron Devices, vol.39 , pp.1704-1710, July, 1992.
[2.12] D. J. Frank, Y. Taur, and H. S. P. Wong, “Generalized scale length for two-dimension effects in MOSFETs,"IEEE Electron Device Lett., vol.19, pp.385-387, Oct. ,1998.
[2.13] S. H. Oh, D. Monroe, and J. M. Hergenrother, “Analytic description of short-channel effects in fully-depleted double-gate and cylindrical, surrounding-gate MOSFETs,"IEEE Electron Device Lett., vol.21, pp.445 -447, Sept.,2000.
[2.14] Q. Chen, B. Agrawal, and J. D. Meindl, “A comprehensive analytical subthreshold swing S model for double-gate MOSFETs, IEEE Trans. Electron Devices, vol.49 , pp.1086-1090, June, 2002.
[2.15] Q. Chen, E. M. Harrell, and J. D. Meindl, “A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs,"IEEE Trans. Electron Devices, vol.50, pp.1631-1637, July, 2003.
[2.16] X. Liang, and Y. Taur, “A 2-D analytical solution for SCEs in DG MOSFETs, "IEEE Trans. Electron Devices, vol. 51 , pp.1385-1391, August, 2004.
[2.17] Y. Taur and T. H. Ning, Fundamental of Modern VLSI Devices. Cambridge, U. K.﹕Cambridge Univ. Press, 1998.
[2.18] Y. Taur, S. Cohen, S. Wind, T. Lii, C. Hsu, D. Quinlan, C. A. Chang, D. Buchanan, P. Agnello, Y. J. Mii, C. Reeves, A. Acovic, and V. Keasan, “Experimental 0.1-μm p-channel MOSFET with p+-polysilicon gate on 35- gate oxide,"IEEE Electron Device Lett., vol.14, pp.304-306, June,1993.
[2.19] MEDICI. Two-dimensional device simulation program, Synopsys, 2003.
[3.1] The National Technology Roadmap for Semiconductors, 3rd edition, Semiconductor Industry Association, San Jose, CA, 1997.
[3.2] SIA et al, International Technology Roadmap for Semiconductors (ITRS), 2001 edition, public.itrs.net
[3.3] H. R. Huff, and D. C. Gilmer, (Eds.) “High Dielectric Constant Materials VLSI MOSFET Applications", 2005.
[3.4] J. S. Yuan, and J. J. Liou, “Semiconductor Device Physics and Simulation", Plenum Publishing Corporation, May 1 1998.
[3.5] J. J. Liou, A. Ortiz-Conde, and F. Garcia-Sanchez, “Analysis and Design of MOSFET,s Modeling, Simulation, and Parameter Extration", Kluwer Azademic Publishers.
[3.6] S. H. Lo, D. A. Buchanan, Y. Taur, and W. Wang, “Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET,s", IEEE Electron Device Lett., vol.18, no.5 pp.209-211, May ,1997.
[3.7] H. S. Momose, M. Ono, T. Yoshitomi, T. Ohguro, S.-I Nakamura, M. Saito, and H. Iwai, “1.5 nm direct-tunneling gate oxide Si MOSFET,s", IEEE Trans. Electron Devices, vol.43, pp.1233-1242, August, 1996.
[3.8] C. Chaneliere, S. Four, J. L. Autran, R. A. B. Devine, and N. P. Sandler, “Properties of amorphous and crystalline Ta2O5 thin films deposited on Si from a Ta(OC2H5)5 precursor", J. Appl. Phys., vol.83, no.9, pp.4823-4829, May,1998.
[3.9] S. A. Campbell, D. C. Gilmer, X.-C. Wang, M.-T. Hsieh, H.-S. Kim, W. L. Gladfelter, and J. Yan, “MOSFET transistors fabricated with high permittivity TiO2 dielectrics", IEEE Trans. Electron Devices, vol.44, pp.104-109, Jan., 1997.
[3.10] Y. Harada, M. Niwa, S. Lee, and D. L. Kwong,“Specific structural factors influencing on reliability of CVD-HfO2", Symp VLSI Tech Dig, 2002: 26-7.
[3.11] J. H. Lee, Y. S. Kim, H. S. Jung, N. I. Lee, H. K. Kang, et al, “Poly-Si gate CMOSFET with HfO2-Al2O3 laminate gate dielectric for low power applications", Symp VLSI Tech Dig, 2002.
[3.12] G. C. -F. Yeap, S. Krishnam, and M. R. Lin, “Fringing-induced barrier lowing (FIBL) in sub-100nm MOSFETs with high-k gate dielectrics"Electronics Lett., vol.34, no.11 pp.1150-1152, 1998.
[3.13] A. Inani, V. R. Rao, B. Cheng, M. Cao, P. V. Voorde, W. M. Greene, and J. C. S. Woo, “Performance considerations in using high-k dielectric for deep sub-micron MOSFETs", in Ext. Abstr. SSDM98, pp.94-95,1998.
[3.14] B. Cheng, M. Cao, R. Rao, A. Inani, P. V. Voorde, W. M. Greene, J. M. C. Stork, Z. Yu, P. M. Zeitzoff, and J. C. S. Woo, “The impact of high-k gate dielectric and metal gate electrodes on sub-100nm MOSFETs", IEEE Trans. Electron Devices, vol.46, pp.1537-1543, July ,1999.
[3.15] J. Zhang, J. S. Yuan, and Y. Ma, “Modeling short channel effect on high.k and staced-gate MOSFETs,"Solid-State Electronics, vol.44, pp.2089-2091, November , 2000.
[3.16] X. Liu, J. Kang, L. Sun, R. Han, and Y. Wang, “Threshold voltage model for MOSFETs with high-k gate dielectrics", IEEE Electron Device Lett., vol.23, pp.270-272, May ,2002.
[3.17] X. Liang, and Y. Taur, “A 2-D analytical solution for SCEs in DG MOSFETs, "IEEE Trans. Electron Devices, vol. 51 , pp.1385-1391, August, 2004.
[3.18] Q. Chen, L. Wang, J. D. Meindl, “Fringe-induced barrier lowering (FIBL) induced threshold voltage model for double-gate MOSFETs,"Solid-State Electronics, vol.49, pp.271-274, February , 2005.
[3.19] MEDICI. Two-dimensional device simulation program, Synopsys, 2003.
[3.20] D. J. Frank, Y. Taur, and H. S. P. Wong, “Generalized scale length for two-dimension effects in MOSFETs,"IEEE Electron Device Lett., vol.19, pp.385-387, Oct., 1998.
[3.21] Z.-H. Liu, C. Hu, J.-H. Huang, T.-Y. Chan, M.-C. Jeng, P. K. Ko, and Y. C. Cheng, “Threshold voltage model for deep- submicron MOSFETs", IEEE Trans. Electron Devices, vol.40, pp.86-95, January, 1993.
[3.22] R. H. Yan, A. Ourmazed, and K. F. Lee, “Scaling the Si MOSFET ﹕From bulk to SOI to bulk,"IEEE Trans. Electron Devices, vol.39 , pp.1704-1710, July, 1992.
[3.23] D. J. Frank, H. –S. P. Wong, “Analysis of the design space available for high-k gate dielectrics in nanoscale MOSFETs", Superlattices Microstruct , pp.485-491, 2000.
[3.24] X. Zhou, K. Y. Lim, and D. Lim, “A simple and unambiguous definition of threshold voltage and its implications in deep-submicron MOS device modeling”, IEEE Trans. Electron Devices, vol.46 , pp.807-809, April, 1999.
[3.25] C. H. Lai, L. C. Hu, H. M. Lee, L. J. Do,and Y. C. King, “New stack gate insulator structure reduce FIBL effect obviously ”, IEEE International Symposium on VLSI Technology, Systems, and Applications, pp.216-219, 2001.
[4.1] D. J. Frank, R. H. Dennard, E. Nowak, D. M. Solomon, Y. Taur, and H. Wong, “Device scaling limits of Si MOSFET’s and their application dependencies", Proc. IEEE, vol.89, no.3, pp.259-288, Mar., 2001.
[4.2] D. J. Frank, S. E. Laux, and M. V. Fischetti, “Monte Carlo simulation of a 30-nm dual-gate MOSFET: How short can Si go ?", in Int. Electron Device Meeting Tech. Dig., pp.553-556, 1992.
[4.3] S. Venkatesan, G. W. Neudeck, and R. F. Pierret, “Dual gate operation and volume inversion in n-channel SOI MOSFET’s", IEEE Electron Device Letter, vol.13, no. 1, pp.44-46, Jan., 1992.
[4.4] K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, Y. Arimoto, and T. Itoh, “Analytical surface potential expression for thin-film double-gate SOI MOSFET’s", Solid State Electron., vol.37, pp.327-332, 1994.
[4.5] K. Suzuki, S. Satoh, T. Tanaka, and S. Ando, “Analytical models for symmetric thin-film double-gate silicon-on-insulator metal-oxide-semiconductor field-effect transistors", Jpn. J. Appl. Phy., vol.32, pp.4916-4922, 1993.
[4.6] K. Suzuki, Y. Tosaka, T. Tanaka, H. Horie, and Y. Arimoto, “Scaling theory of double-gate SOI MOSFET’s", IEEE Trans. Electron Devices, vol.40, no.12, pp.2326-2329, Dec., 1993.
[4.7] Y. Tosaka, K. Suzuki, H. Horie, and T. Sugii, “Scaling-parameter-dependent model for subthreshold swing S in double-gate SOI MOSFET’s", IEEE Electron Device Lett., vol. 15, no.11, pp.466-468, Nov., 1994.
[4.8] S. Horiuchi and J. Yamaguchi, “Diffusion of boron in silicon through oxide layer", Jpn. J. Appl. Phys., vol.1, pp.314–323, 1962.
[4.9] J. R. Pfiester, L. C. Parrilo, and F. K. Baker, “A physical model for boron penetration through thin gate oxide from P polysilicon gates”, IEEE Electron Device Lett., vol.11, pp. 247–249, 1990.
[4.10] W. Long, H. Ou, J. -M. Kuo, and K.K. Chin, “Dual material gate (DMG) field effect transistor", IEEE Trans. Electron Devices, vol.46, no.5, pp.865-870, May,1999.
[4.11] X. Zhou and W. Long, “A novel hetero-material gate (HMG) MOSFET for deep-submicron ULSI technology,” IEEE Trans. Electron Devices, vol. 45, no. 12, pp. 2546–2548, Dec. 1998.
[4.12] M. J. Kumar and A. Chaudhry, “Two-dimensional analytical modeling of fully depleted dual-material gate (DMG) SOI MOSFET and evidence for diminished short-channel effects,” IEEE Trans. Electron Devices, vol.15, no. 4, pp. 569–574, Apr. 2004.
[4.13] U. K. Mishra, A. S. Brown, and S. E. Rosenbaum, “DC and RF performance of 0.1-_mgate length Al As=Ga In As pseudomorphic HEMT,” in Int. Electron Devices Meeting Tech. Dig., pp.180–183, 1988.
[4.14] M. Saxena, S. Haldar, M. Gupta, and R. S. Gupta, “Physics-based an-alytical modeling of potential and electrical field distribution in Dual Material Gate (DMG)-MOSFET for improved hot electron effect and carrier transport efficiency,” IEEE Trans. Electron Devices, vol.49, no.11, pp. 1928–1938, Nov., 2002.
[4.15] A. Chaudhry, and M. J. Kumar, “Investigation of the novel attributes of a fully depleted dual-material gate SOI MOSFET,"IEEE Trans. Electron Devices, vol. 51, no. 9, pp.1463–1467, 2004 .
[4.16] G. V. Reddy, and M. J. Kumar, “A new dual-material double-gate (DMDG) nanoscale SOI MOSFET-Two-dimensional analytical modeling and simulation,"IEEE Trans. On Nanotechnology, vol.4, no.2, pp.260–268, March, 2005.
[4.17] MEDICI, Two-dimensional device simulation program, Synopsis, 2003.
[4.18] R. H. Yan, A. Ourmazed, and K. F. Lee, “Scaling the Si MOSFET: From bulk to SOI to bulk,"IEEE Trans. Electron Devices, vol.39, pp.1704–1710, July, 1992 .
[4.19] X. Zhou, “Exploring the novel characteristics of hetero-material gate field-effect transistors (HMGFET’s) with gate-material engineering,” IEEE Trans. Electron Devices, vol.47, no.1, pp. 113–120, Jan., 2000.
[5.1] Y. Taur and T. H. Ning , Fundamentals of Modern VLSI Devices. New York, New York: Cambridge, 1998.
[5.2] F. Stern, “Self-consistent results for n-type Si inversion layers", Phys. Rev. B, vol. 5, pp. 4891–4899, Nov., 1972.
[5.3] F. Stern and W. E. Howard, “Properties of semiconductor surface inversion layers in the electric quantum limit", Phys. Rev., vol.163, pp.816–835, Nov., 1967.
[5.4] B. Majkusiak, T. Janik, and J. Walczak, “Semiconductor thickness effects in the double- gate SOI MOSFET", IEEE Transactions on Electron Devices, vol.45, no.5, pp.1127-1134, 1998.
[5.5] G. Baccarani and S. Reggiani “A compact double-gate MOSFET model comprising quantum-mechanical and nonstatic effects", IEEE Transactions on Electron Devices; vol.46, no.8, pp.1656-1666, 1999.
[5.6] D. J. Frank, S. E. Laux, and M. V. Fischetti, “Monte Carlo simulation of a 30 nm dual-gate MOSFET: how short can Si go? ", IEEE International Electron Device Meeting, pp.553-556, 1992.
[5.7] H. -S. P Wong., D. J. Frank, and P. M. Solomon, “Device design consideration for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation", IEEE International Electron Device Meeting; pp.407-410, 1998.
[5.8] L. Ge, and J. G. Fossum, “Analytical modeling of quantization and volume inversion in thin Si-film DG MOSFETs", IEEE Transactions on Electron Devices; vol.49, no.2, pp.287-294, 2002.
[5.9] R. G. Winter, Quantum Physics. Belmont, CA: Wadsworth, 1979.
[5.10] Q. Chen, E.M. Harrell, and J.D. Meindl, “A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs", IEEE Transactions on Electron Devices, vol.50, no.7, pp.1631-1637, 2003.
[5.11] Q. Chen, K. A. Bowman, E.M. Harrell, and J.D. Meindl, “Double jeopardy in the nanoscale court ? – Modeling the scaling limits of double-gate MOSFETs with physics-based compact short-channel models of threshold voltage and subthreshold swing", IEEE Circuits and Devices Magazine, vol.19, no.1, pp.28-34, 2003.
[5.12] D. J. Frank, Y. Taur, and H.-S. P. Wong, “Generalized scale length for two-dimensional effects in MOSFETs”, IEEE Electron Device Lett., vol.19, pp. 385–387, Oct., 1998.
[5.13] R. H. Yan, A. Ourmazd, and K. F. Lee, “Scaling the Si MOSFET: from bulk to SOI to bulk”, IEEE Trans. Electron Devices, vol.39, pp.1704–1710, July, 1992.
[5.14] K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, and Y. Arimoto, “Scaling theory for double-gate SOI MOSFETs”, IEEE Trans. Electron Devices, vol. 40, pp.2326–2329, Dec., 1993.
[5.15] J. Wang, P. M. Solomon, and M. Lundstrom, “A General Approach for the Performance Assessment of Nanoscale Silicon FETs", IEEE Trans. Electron Devices, vol.51, no.9, pp.1366-1370, SEPTEMBER, 2004.
[5.16] C. P. Auth and J. D. Plummer, “Scaling theory for cylindrical, fully- depleted, surrounding-gate MOSFETs,” IEEE Electron Device Lett., vol.18, pp.74–76, Feb., 1997.
[5.17] APSYS. Crosslight Software Inc., 2004.
連結至畢業學校之論文網頁點我開啟連結
註: 此連結為研究生畢業學校所提供,不一定有電子全文可供下載,若連結有誤,請點選上方之〝勘誤回報〞功能,我們會盡快修正,謝謝!
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top